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yosys/tests/arch/quicklogic
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Krystine Sherwin 7f12d0ba95 QLF_TDP36K: more basic tdp/sdp sim tests 
Adds TDP submodule to generator.
Adds shorthand expected signal to testbench (mostly to make it easier when I look at the vcd dump to figure out what I did wrong in tests).
2023-12-04 15:52:03 +01:00
..
pp3 quicklogic: Move pp3 tests one level down 2023-12-04 15:52:02 +01:00
qlf_k6n10f QLF_TDP36K: more basic tdp/sdp sim tests 2023-12-04 15:52:03 +01:00
.gitignore quicklogic: Add .gitignore file for test outputs. 2021-03-23 17:35:00 +01:00