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yosys/tests/arch/quicklogic
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Krystine Sherwin 3d08ed216d QLF_TDP36K: parameterised sim test gen 
Also limited to 16 tests per file to allow parallelism.
Previous tests are converted to new test format with no sim test steps.
2023-12-04 15:52:03 +01:00
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pp3 quicklogic: Move pp3 tests one level down 2023-12-04 15:52:02 +01:00
qlf_k6n10f QLF_TDP36K: parameterised sim test gen 2023-12-04 15:52:03 +01:00
.gitignore quicklogic: Add .gitignore file for test outputs. 2021-03-23 17:35:00 +01:00