2167 commits

Author	SHA1	Message	Date
Eddie Hung	4aa505d1b2	Merge pull request #1344 from YosysHQ/eddie/ice40_signed_macc ... ice40_dsp to allow signed multipliers	2019-09-01 10:11:33 -07:00
Miodrag Milanovic	fa5065e9b5	Fix select command error msg, fixes issue #1081	2019-09-01 11:00:09 +02:00
Eddie Hung	17b77fd411	Missing dep for test_pmgen	2019-08-30 14:01:07 -07:00
Eddie Hung	999fb33fd0	Merge pull request #1340 from YosysHQ/eddie/abc_no_clean ... abc9 to not call "clean" at end of run (often called outside)	2019-08-30 12:27:09 -07:00
Eddie Hung	c1459bc748	Do not restrict multiplier to unsigned	2019-08-30 12:22:14 -07:00
Eddie Hung	6e475484b2	Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl	2019-08-30 09:37:32 -07:00
Eddie Hung	18cabe9370	Output has priority over input when stitching in abc9	2019-08-29 17:24:03 -07:00
Eddie Hung	3e0f73c3df	abc9 to not call "clean" at end of run (often called outside)	2019-08-29 12:12:59 -07:00
Eddie Hung	1467761060	Fix typo that's gone unnoticed for 5 months!?!	2019-08-29 10:33:28 -07:00
Eddie Hung	4eb5847dbd	Cleanup	2019-08-28 18:10:33 -07:00
Eddie Hung	0af64df10c	Account for D port being a constant	2019-08-28 15:32:38 -07:00
Eddie Hung	fc727fa5c9	Merge pull request #1334 from YosysHQ/clifford/async2synclatch ... Add $dlatch support to async2sync	2019-08-28 12:36:06 -07:00
Eddie Hung	52c4655de3	No need to replace Q of slice since $shiftx is autoremove-d	2019-08-28 11:06:11 -07:00
Eddie Hung	11e3eb1009	More cleanup	2019-08-28 10:19:35 -07:00
Eddie Hung	86b538bd02	More cleanup	2019-08-28 10:11:09 -07:00
Eddie Hung	c4d1bd988b	Do not use default_params dict, hardcode default values, cleanup	2019-08-28 10:06:40 -07:00
Eddie Hung	c3e9627afe	Always generate if no match	2019-08-28 09:54:56 -07:00
Eddie Hung	0ebe2c9831	Rename test_pmgen arg xilinx_srl.{fixed,variable}	2019-08-28 09:27:03 -07:00
Eddie Hung	ba5d81c7f1	Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl	2019-08-28 09:21:03 -07:00
Clifford Wolf	47ffbf554e	Fix typo ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-28 10:06:42 +02:00
Clifford Wolf	0fda0e821c	Add "paramap" pass ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-28 10:03:27 +02:00
Clifford Wolf	c499dc3e73	Add $dlatch support to async2sync ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-28 09:45:22 +02:00
Clifford Wolf	70c0cddb1e	Merge pull request #1325 from YosysHQ/eddie/sat_init ... In sat: 'x' in init attr should be ignored	2019-08-28 00:18:14 +02:00
Eddie Hung	28133432be	Ignore all 1'bx in (* init *)	2019-08-27 09:24:59 -07:00
Marcin Kościelnicki	5fb4b12cb5	improve clkbuf_inhibit propagation upwards through hierarchy	2019-08-27 17:26:47 +02:00
Eddie Hung	9172d4a674	Missing close bracket	2019-08-26 21:02:52 -07:00
Eddie Hung	6b5e65919a	Revert "In sat: 'x' in init attr should not override constant" ... This reverts commit 2b37a093e9.	2019-08-26 17:52:57 -07:00
Eddie Hung	54422c5bb4	Remove leftover header	2019-08-26 17:51:13 -07:00
Eddie Hung	e95fb24574	Improve xilinx_srl.fixed generate, add .variable generate	2019-08-26 17:49:08 -07:00
Eddie Hung	45c34c87ee	Account for maxsubcnt overflowing	2019-08-26 17:48:54 -07:00
Eddie Hung	b32d6bf403	Add xilinx_srl_pm.variable to test_pmgen	2019-08-26 17:44:57 -07:00
Eddie Hung	e574edc3e9	Populate generate for xilinx_srl.fixed pattern	2019-08-26 14:21:17 -07:00
Eddie Hung	cf9e017127	Add xilinx_srl_fixed, fix typos	2019-08-26 14:20:06 -07:00
Eddie Hung	a098205479	Merge branch 'master' into mwk/xilinx_bufgmap	2019-08-26 13:25:17 -07:00
Eddie Hung	7911143827	Create new $__XILINX_SHREG_ cell for variable length too	2019-08-23 18:15:49 -07:00
Eddie Hung	a048fc93e8	Do not allow Q of last cell of variable length SRL to be (* keep *)	2019-08-23 18:15:24 -07:00
Eddie Hung	ee9f6e6243	Also add first.Q to chain_bits since variable length	2019-08-23 18:14:06 -07:00
Eddie Hung	70ce3d0670	Do not enforce !EN_POLARITY on $dffe	2019-08-23 18:11:28 -07:00
Eddie Hung	188b49378a	Create new cell for fixed length SRL	2019-08-23 17:25:30 -07:00
Eddie Hung	e081303ee8	Cleanup FDRE matching	2019-08-23 17:23:52 -07:00
Eddie Hung	54488cfb82	Oops don't need a finally block	2019-08-23 16:39:37 -07:00
Eddie Hung	83e2d87fb8	Keep track of bits in variable length chain, to check for taps	2019-08-23 16:21:10 -07:00
Eddie Hung	f2d4814284	Don't forget $dff has no EN	2019-08-23 16:14:57 -07:00
Eddie Hung	2217d926a9	Same for variable length	2019-08-23 16:13:16 -07:00
Eddie Hung	b1caf7be5e	Filter on en_port for fixed length	2019-08-23 16:09:46 -07:00
Eddie Hung	513af10d77	Check clock is consistent	2019-08-23 15:18:26 -07:00
Eddie Hung	c762618783	Fix last_cell.D	2019-08-23 15:08:49 -07:00
Eddie Hung	ca5de78e76	Revert "Add a unique argument to pmgen's nusers()" ... This reverts commit 1d88887cfd.	2019-08-23 15:04:00 -07:00
Eddie Hung	e85e6e8d45	Revert "Fix polarity" ... This reverts commit 9cd23cf0fe.	2019-08-23 15:03:42 -07:00
Eddie Hung	9cd23cf0fe	Fix polarity	2019-08-23 14:49:34 -07:00