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13602 commits

Author SHA1 Message Date
Miodrag Milanovic
f806987d58 Add PR template 2024-05-08 12:00:18 +02:00
Akash Levy
818fd2e0fa
Merge branch 'YosysHQ:main' into master 2024-05-08 02:23:09 -07:00
Miodrag Milanovic
561618002a Next dev cycle 2024-05-08 09:02:50 +02:00
Miodrag Milanovic
c1ad37779e Release version 0.41 2024-05-08 08:52:10 +02:00
Miodrag Milanovic
7ab43dc1b7 Update ABC with Windows fixes 2024-05-08 08:30:30 +02:00
Catherine
1ac00088a6
Merge pull request #4380 from whitequark/cxxrtl-metadata-compression
cxxrtl: reduce stack space used by the `debug_info()` function
2024-05-08 05:48:29 +01:00
Catherine
6e003e1af6 cxxrtl: minimize stack space consumed by debug_info().
This commit uses parameter packs to sink `debug_item()` construction
into the `debug_info()`-specific `add()` overload. This makes the stack
space use sub-linear in typical case rather than linear (which is still
the worst case). Oddly, the stack slots that get allocated now are all
for the `0` literal for `lsb_offset`. This could be fixed by allocating
numbers statically but the existing reduction in stack use of ~98% for
a representative example (Minerva SoC) should be enough.
2024-05-08 03:37:14 +00:00
Catherine
80798daf53 cxxrtl: reduce stack space consumed by debug_info() further.
Before this commit, this function would create a temporary `std::string`
per debug item (and scope). After this commit, an additional overload is
used to push that down the call stack. This reduces stack usage by
about 50% more on top of the previous commit.
2024-05-08 02:55:17 +00:00
Catherine
9134cd1928 cxxrtl: reduce stack space consumed by debug_info().
Before this commit, the creation of (constant) attribute maps caused
`debug_info()` (which is built with `__attribute__((optnone))`) to
consume large amounts of stack space; up to tens of megabytes. This
caused problems particularly on macOS, where the default stack size
is 512 KiB.

After this commit, `std::map` objects are no longer created inline in
the `debug_info()` function, but are compiled to and then expanded from
a string literal in a subroutine call. This reduces stack space usage
by about 50%.
2024-05-08 02:55:17 +00:00
Catherine
43ddd89ba5 cxxrtl: fix escape_c_string hex literal fiasco.
In C and C++, a `\x` escape sequence consumes as many hexadecimal digits
as there are available, so it is not composable with arbitrary alnum
characters afterwards. An octal escape sequence like `\000` always has
fixed width, avoiding an issue where `\x01c` and `\x1c` produce the same
string.
2024-05-08 02:55:17 +00:00
Akash Levy
2e21078a83
Merge branch 'YosysHQ:main' into master 2024-05-07 18:21:19 -07:00
Ethan Mahintorabi
c039da2ec1
renames variables for more code clairty
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-05-08 01:09:52 +00:00
Ethan Mahintorabi
a2c1b268d9
frontend: Fixes verific import around range order
Test Case
```
module packed_dimensions_range_ordering (
    input  wire [0:4-1] in,
    output wire [4-1:0] out
);
  assign out = in;
endmodule : packed_dimensions_range_ordering

module instanciates_packed_dimensions_range_ordering (
    input  wire [4-1:0] in,
    output wire [4-1:0] out
);
  packed_dimensions_range_ordering U0 (
      .in (in),
      .out(out)
  );
endmodule : instanciates_packed_dimensions_range_ordering
```

```
// with verific, does not pass formal
module instanciates_packed_dimensions_range_ordering(in, out);
  input [3:0] in;
  wire [3:0] in;
  output [3:0] out;
  wire [3:0] out;

  assign out = { in[0], in[1], in[2], in[3] };
endmodule

// with surelog, passes formal
module instanciates_packed_dimensions_range_ordering(in, out);
  input [3:0] in;
  wire [3:0] in;
  output [3:0] out;
  wire [3:0] out;

  assign out = in;
endmodule
```

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-05-08 01:00:06 +00:00
Catherine
7294d8b5af cxxrtl: fix close of invalid fd in spool destructor. 2024-05-08 00:46:10 +00:00
github-actions[bot]
ce45011275 Bump version 2024-05-08 00:13:52 +00:00
Roland Coeurjoly
6d181c29ce Checking different cases for abc 2024-05-08 00:32:18 +02:00
Roland Coeurjoly
fdbe8714c9 Check that abc is checkout out as a git repo 2024-05-08 00:32:18 +02:00
Roland Coeurjoly
67d4c8bba6 Use $< to refer to the first prerequisite listed in the rule 2024-05-08 00:32:18 +02:00
Roland Coeurjoly
09b9aa83c9 Add YosysHQ/abc as a submodule located in abc 2024-05-08 00:32:18 +02:00
Miodrag Milanović
c9d87d5e7b
Merge pull request #4377 from jix/smtbmc-incremental-improvements
smtbmc: Improvements for --incremental and .yw fixes
2024-05-07 21:35:10 +02:00
N. Engelhardt
8735107c60
Merge pull request #4321 from YosysHQ/fix_read_verilog_defaults
read_verilog: Add missing defaults for flags
2024-05-07 21:11:42 +02:00
Krystine Sherwin
df95ea824b read_verilog: Add missing defaults for flags
Fix for YosysHQ/sby#103
2024-05-07 20:25:36 +02:00
Jannis Harder
a52088b6af smtbmc: Improvements for --incremental and .yw fixes
This extends the experimental incremental JSON API to allow arbitrary
smtlib subexpressions, defining smtlib constants and to allow access of
signals by their .yw path.

It also fixes a bug during .yw writing where values would be re-emitted
in later cycles if they have no newer defined value and a potential
crash when using --track-assumes.
2024-05-07 17:57:37 +02:00
Miodrag Milanovic
71f2540cd8 docs conf.py change Release -> Version 2024-05-07 15:55:52 +02:00
Miodrag Milanovic
b4034a881e Keep docs version in conf.py 2024-05-07 15:35:25 +02:00
Miodrag Milanović
90dd508156
Merge pull request #4372 from YosysHQ/krys/docs_version_number
Docs: Set release to YOSYS_VER
2024-05-07 09:15:51 +02:00
Akash Levy
0e77a03359
Merge branch 'YosysHQ:main' into master 2024-05-06 21:11:06 -07:00
Akash Levy
89439199e8 Fix 2024-05-06 21:09:32 -07:00
Krystine Sherwin
6eb49ee9e8
Makefile: Export YOSYS_VER only for make docs 2024-05-07 10:23:22 +12:00
Emil J
68c7fc4c91
Merge pull request #4300 from YosysHQ/cellmatch
cellmatch: New pass for picking out standard cells automatically
2024-05-06 15:12:37 +02:00
Akash Levy
261bc561fa Allow for gzip magic in stat 2024-05-05 04:21:47 -07:00
Krystine Sherwin
fe27240b3a
Makefile: Export YOSYS_VER 2024-05-04 16:51:38 +12:00
Krystine Sherwin
bb0be8c7a2
Docs: Set release to YOSYS_VER
If building from read the docs, and the current build is "latest", add `-dev` to the version string.
Requires `YOSYS_VER` to be exported by .readthedocs.yaml.
2024-05-04 16:51:29 +12:00
github-actions[bot]
0f9ee20ea2 Bump version 2024-05-04 00:16:00 +00:00
Emil J. Tywoniak
e939182e68 cellmatch: add comments 2024-05-03 16:42:41 +02:00
Martin Povišer
b143e5678f cellmatch: Rename the special design to $cellmatch 2024-05-03 16:42:41 +02:00
Martin Povišer
913bc87c44 cellmatch: Add test 2024-05-03 16:42:41 +02:00
Martin Povišer
c0e68dcc4d cellmatch: Add debug print 2024-05-03 16:42:41 +02:00
Martin Povišer
6a9858cdad cellmatch: Delegate evaluation to ConstEval 2024-05-03 16:42:41 +02:00
Martin Povišer
86e1080f05 cellmatch: New pass 2024-05-03 16:42:41 +02:00
Emil J
2631c7e918
Merge pull request #4365 from widlarizer/techmap-chtype-test
techmap: add dynamic cell type test
2024-05-03 16:25:42 +02:00
Emil J. Tywoniak
a833f05036 techmap: add dynamic cell type test 2024-05-03 13:53:49 +02:00
Martin Povišer
6ff4ecb2b4 techmap: Remove techmap_chtype from the result 2024-05-03 13:33:28 +02:00
Martin Povišer
fc82251105 techmap: Support dynamic cell types 2024-05-03 13:33:28 +02:00
Akash Levy
2a8575abb2 Update verific to O3 opt 2024-05-03 03:34:36 -07:00
Akash Levy
bf8ab97890 Slim yosys 2024-05-03 03:29:42 -07:00
Akash Levy
cc5e893db8 Add noclean option to submod for speedup 2024-05-02 06:12:09 -07:00
Akash Levy
e62bc102ca Update Verific 2024-05-01 05:43:32 -07:00
Akash Levy
fbf87b2b23 Update Makefile 2024-04-30 05:21:36 -07:00
Akash Levy
810a11b6bc Fix introduced typo 2024-04-29 22:25:17 -07:00