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Code Activity
12740 commits 123 branches 59 tags 44 MiB
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425 commits

Author SHA1 Message Date
Eddie Hung
7e7965ca7b Trim shiftx_width when upper bits are 1'bx 2019-08-21 18:43:17 -07:00
Eddie Hung
ed7be3e6b6 Add comment 2019-08-21 17:36:38 -07:00
Eddie Hung
15188033da Add variable length support to xilinx_srl 2019-08-21 17:34:40 -07:00
Eddie Hung
6d76ae4c65 Rename pattern to fixed 2019-08-21 15:46:58 -07:00
Eddie Hung
b0a3b430bf attribute -> attr 2019-08-21 15:44:07 -07:00
Eddie Hung
61b4d7ae13 Use Cell::has_keep_attribute() 2019-08-21 15:41:46 -07:00
Eddie Hung
6fa9e03e4c xilinx_srl to support FDRE and FDRE_1 2019-08-21 15:35:29 -07:00
Eddie Hung
3c8e8521a6 Fix polarity of EN_POL 2019-08-21 14:42:11 -07:00
Eddie Hung
a980f0d4be Add CLKPOL == 0 2019-08-21 14:35:40 -07:00
Eddie Hung
1c7d721558 Reject if not minlen from inside pattern matcher 2019-08-21 14:26:24 -07:00
Eddie Hung
cab2bd083e Get wire via SigBit 2019-08-21 13:47:47 -07:00
Eddie Hung
52fea5b658 Respect \keep on cells or wires 2019-08-21 13:42:03 -07:00
Eddie Hung
5ce0c31d0e Add init support 2019-08-21 13:05:10 -07:00
Eddie Hung
df53fe12e7 Fix spacing 2019-08-21 12:54:11 -07:00
Eddie Hung
0250712486 Initial progress on xilinx_srl 2019-08-21 12:50:49 -07:00
Miodrag Milanovic
948b6f91a1 Fix test_pmgen deps 2019-08-21 17:00:24 +02:00
Eddie Hung
4cc74346f1 Fix compile error 2019-08-20 20:27:05 -07:00
Eddie Hung
9b9d759451 Fix copy-paste typo 2019-08-20 20:18:51 -07:00
Eddie Hung
b7a48e3e0f Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-20 20:18:17 -07:00
Clifford Wolf
d0117d7d12
Merge branch 'master' into clifford/pmgen 2019-08-20 11:39:23 +02:00
Clifford Wolf
1e3dd0a2da Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen 2019-08-19 13:04:06 +02:00
Miodrag Milanovic
dbe3cb9708 Ignore all generated headers for pmgen pass 2019-08-18 10:49:17 +02:00
Clifford Wolf
f3405fb048 Refactor pmgen rollback mechanism 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-17 13:54:18 +02:00
Clifford Wolf
318ae0351c Improvements in "test_pmgen -generate" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-17 13:53:55 +02:00
Clifford Wolf
f95853c822 Add pmgen "fallthrough" statement 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-17 11:29:37 +02:00
Eddie Hung
cd5a372cd1 Add help() call 2019-08-16 13:00:12 -07:00
Clifford Wolf
64bd414e54 Minor bugfix in "test_pmgen -generate" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-16 14:35:13 +02:00
Clifford Wolf
20910fd7c8 Add pmgen finish statement, return number of matches 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-16 14:16:35 +02:00
Clifford Wolf
f45dad8220 Redesign pmgen backtracking for recursive matching 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-16 13:47:50 +02:00
Clifford Wolf
c710df181c Add pmgen "generate" feature 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-16 13:26:36 +02:00
Clifford Wolf
4a57b7e1ab Refactor demo_reduce into test_pmgen 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-16 11:47:51 +02:00
Clifford Wolf
016036f247 Add doc for pmgen semioptional statement, Add pmgen changes to CHANGELOG 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-15 23:02:37 +02:00
Clifford Wolf
969ab9027a Update pmgen documentation 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-15 22:48:13 +02:00
Clifford Wolf
eb80d3d43f Change pmgen default rule to reject, switch peepopt behavior to accept 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-15 22:47:59 +02:00
Eddie Hung
c320abc3f4 xilinx_dsp to be sensitive to keep attribute 2019-08-15 12:34:11 -07:00
Eddie Hung
96ee7b9cf7 Simplify 2019-08-15 12:30:46 -07:00
Eddie Hung
27d5df9467 ffH -> ffFJKG 2019-08-15 12:19:34 -07:00
Clifford Wolf
03f98d9176 Add demo_reduce pass to demonstrace recursive pattern matching 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-15 18:36:39 +02:00
Clifford Wolf
73bf453929 Improvements in pmgen for recursive patterns 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-15 18:35:56 +02:00
Eddie Hung
aad97168b0 Fixes for reverting SigSpec helper functions 2019-08-14 10:22:33 -07:00
Eddie Hung
2f04beeeb5 Perform C -> PCIN optimisation after pattern matcher 2019-08-13 17:11:35 -07:00
Eddie Hung
1b0e68db94 Revert changes to RTLIL::SigSpec methods 2019-08-13 17:09:28 -07:00
Eddie Hung
0597a3ea23 Rename to XilinxDspPass 2019-08-13 10:23:07 -07:00
Eddie Hung
12c692f6ed Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" 
This reverts commit c851dc1310, reversing
changes made to f54bf1631f.
 2019-08-12 12:06:45 -07:00
David Shah
f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" 2019-08-10 17:14:48 +01:00
Eddie Hung
ab1d63a565 Check nusers of DSP output, not whole flop 2019-08-09 17:35:13 -07:00
Eddie Hung
3dd3ab98c2 Improve ice40_dsp for non-fully-32-bit adders 2019-08-09 17:23:12 -07:00
Eddie Hung
dfc878deb4 Another filter -> if 2019-08-09 16:23:32 -07:00
Eddie Hung
e83f231927 Cleanup 2019-08-09 15:47:40 -07:00
Eddie Hung
0b5b56c1ec Pack partial-product adder DSP48E1 packing 2019-08-09 15:19:33 -07:00