Eddie Hung
27b7ffc754
ice40: fix ICESTORM_LC process sensitivity
2020-05-12 15:40:48 -07:00
Eddie Hung
4ecae8a673
ice40: fix whitespace
2020-05-12 15:40:13 -07:00
David Shah
95fb3cf487
ecp5: Add missing SERDES parameters
...
Signed-off-by: David Shah <dave@ds0.me>
2020-05-12 21:12:26 +01:00
Dan Ravensloft
5b779f7f4e
intel_alm: direct LUTRAM cell instantiation
...
By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.
While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
2020-05-07 21:03:13 +02:00
Eddie Hung
004999218f
techlibs/common: more robustness when *_WIDTH = 0
2020-05-05 08:01:27 -07:00
Eddie Hung
e6b55e8b38
synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad
2020-05-04 11:44:00 -07:00
whitequark
26cda3c247
gowin,ecp5: remove generated files in make clean.
2020-04-24 23:26:39 +00:00
Dan Ravensloft
4ca5f9799b
intel_alm: cleanup duplication
2020-04-24 11:26:48 +02:00
Dan Ravensloft
3d149aff73
intel_alm: work around a Quartus ICE
2020-04-23 11:03:28 +02:00
Eddie Hung
51ae0f4e20
ecp5: ecp5_gsr to skip cells that don't have GSR parameter again
2020-04-22 17:53:08 -07:00
Eddie Hung
d2d90e4504
xilinx: improve xilinx_dffopt message
2020-04-22 16:25:23 -07:00
Eddie Hung
7f33a0294b
Cleanup use of hard-coded default parameters in light of #1945
2020-04-22 12:02:30 -07:00
Dan Ravensloft
16a3048308
intel_alm: Documentation improvements
2020-04-21 19:38:15 +02:00
Marcelina Kościelnicka
b4d76309e1
Use default parameter value in getParam
...
Fixes #1822 .
2020-04-21 19:09:00 +02:00
David Shah
1664bcda12
ecp5: Force SIGNED ports to be 1 bit
...
Signed-off-by: David Shah <dave@ds0.me>
2020-04-16 16:38:19 +01:00
Marcelina Kościelnicka
53ba3cf718
Fix the truth table for $_SR_* cells.
...
This brings the documented behavior for these cells in line with
$_DFFSR_* and $_DLATCHSR_*, which is that R has priority over S.
The models were already reflecting that behavior.
Also get rid of sim-synth mismatch in the models while we're at it.
2020-04-15 17:17:48 +02:00
Marcelina Kościelnicka
38a0c30d65
Get rid of dffsr2dff.
...
This pass is a proper subset of opt_rmdff, which is called by opt, which
is called by every synth flow in the coarse part. Thus, it never
actually does anything and can be safely removed.
2020-04-15 16:22:37 +02:00
Dan Ravensloft
43cc6bd8a1
synth_intel_alm: VQM support
2020-04-15 16:15:25 +02:00
Dan Ravensloft
2e37e62e6b
synth_intel_alm: alternative synthesis for Intel FPGAs
...
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.
This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2020-04-15 11:40:41 +02:00
whitequark
93ef516d91
Merge pull request #1603 from whitequark/ice40-ram_style
...
ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
2020-04-10 14:51:01 +00:00
Eddie Hung
d61a6b81fc
Merge pull request #1648 from YosysHQ/eddie/cmp2lcu
...
"techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
2020-04-03 16:28:25 -07:00
Eddie Hung
7b38cde2df
cmp2lcu: rename _90_lcu_cmp -> _80_lcu_cmp
2020-04-03 14:28:22 -07:00
Eddie Hung
7b09a20c0c
cmp2lcu: fail if `LUT_WIDTH < 2
2020-04-03 14:28:22 -07:00
Eddie Hung
34c9b83854
synth: only techmap cmp2{lut,lcu} if -lut
2020-04-03 14:28:22 -07:00
Eddie Hung
5b87720b16
synth: use +/cmp2lcu.v in generic 'synth' too
2020-04-03 14:28:22 -07:00
Eddie Hung
2bf03c6ae0
Cleanup +/cmp2lut.v
2020-04-03 14:28:22 -07:00
Eddie Hung
051aefc3c2
synth_xilinx: techmap +/cmp2lut.v and +/cmp2lcu.v in 'coarse'
2020-04-03 14:28:22 -07:00
Eddie Hung
99a32432aa
+/cmp2lcu.v to work efficiently for fully/partially constant inputs
2020-04-03 14:28:22 -07:00
Eddie Hung
f68d723cdc
Refactor +/cmp2lcu.v into recursive techmap
2020-04-03 14:28:22 -07:00
Eddie Hung
8e851badc4
Cleanup
2020-04-03 14:28:22 -07:00
Eddie Hung
da880d5016
Cleanup cmp2lcu.v
2020-04-03 14:28:22 -07:00
Eddie Hung
9b63700678
techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu
2020-04-03 14:28:22 -07:00
Eddie Hung
fffe42d4c1
cmp2lut: comment out unused since 362f4f9
2020-04-03 14:28:04 -07:00
whitequark
763401fc82
ecp5: do not map FFRAM if explicitly requested otherwise.
2020-04-03 05:51:40 +00:00
whitequark
ebee746ad2
ice40: do not map FFRAM if explicitly requested otherwise.
2020-04-03 05:51:40 +00:00
Eddie Hung
5f662b1c43
Merge pull request #1767 from YosysHQ/eddie/idstrings
...
IdString: use more ID::*, make them easier to use, speed up IdString::in()
2020-04-02 11:47:25 -07:00
Eddie Hung
956ecd48f7
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
Marcin Kościelnicki
0ed1062557
simcells.v: Generate the fine FF cell types by a python script.
...
This makes adding more FF types in the future much more manageable.
Fixes #1824 .
2020-04-02 18:37:15 +02:00
Eddie Hung
fdafb74eb7
kernel: use more ID::*
2020-04-02 07:14:08 -07:00
Alberto Gonzalez
fc6b898178
Fix indentation in techlibs/ice40/synth_ice40.cc.
2020-04-01 16:29:56 +00:00
David Shah
beab15b77c
Merge pull request #1794 from YosysHQ/dave/mince-abc9-fix
...
ice40: Map unmapped 'mince' DFFs to gate level
2020-03-21 17:35:27 +00:00
Sylvain Munaut
c15ce5a73e
ice40: Fix typos in SPRAM ABC9 timing specs
...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2020-03-20 22:19:55 +01:00
David Shah
e813624f21
ice40: Map unmapped 'mince' DFFs to gate level
...
Signed-off-by: David Shah <dave@ds0.me>
2020-03-20 20:29:16 +00:00
Marcin Kościelnicki
9b982e929c
xilinx: Mark IOBUFDS.IOB as external pad
2020-03-20 14:37:38 +01:00
Sylvain Munaut
acd9eeef7c
ice40: Fix SPRAM model to keep data stable if chipselect is low
...
According to the official simulation model, and also cross-checked
on real hardware, the data output of the SPRAM when chipselect is
low is kept stable. It doesn't go undefined.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2020-03-14 21:01:42 +01:00
Miodrag Milanovic
acb341745d
Fix invalid verilog syntax
2020-03-14 14:33:44 +01:00
N. Engelhardt
282d331e7e
Merge pull request #1716 from zeldin/ecp5_fix
...
ecp5: remove unused parameter from \$__ECP5_PDPW16KD
2020-03-09 11:04:08 +01:00
N. Engelhardt
8a39a580e1
remove unused parameters
2020-03-06 16:45:36 +01:00
Eddie Hung
69f1555058
ice40: fix specify for ICE40_{LP,U}
2020-03-05 08:11:49 -08:00
Eddie Hung
0930c00f03
ice40: fix implicit signal in specify, also clamp negative times to 0
2020-03-04 15:28:17 -08:00
