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https://github.com/YosysHQ/yosys
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parent
846c79b312
commit
b4d76309e1
2 changed files with 13 additions and 4 deletions
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@ -209,7 +209,7 @@ lut_sigin_done:
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continue;
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LutData lut_d = it_D->second.first;
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Cell *cell_d = it_D->second.second;
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if (cell->hasParam(ID(IS_D_INVERTED)) && cell->getParam(ID(IS_D_INVERTED)).as_bool()) {
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if (cell->getParam(ID(IS_D_INVERTED)).as_bool()) {
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// Flip all bits in the LUT.
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for (int i = 0; i < GetSize(lut_d.first); i++)
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lut_d.first.bits[i] = (lut_d.first.bits[i] == State::S1) ? State::S0 : State::S1;
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@ -249,7 +249,7 @@ lut_sigin_done:
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if (has_s) {
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SigBit sig_S = sigmap(cell->getPort(ID::S));
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LutData lut_s = LutData(Const(2, 2), {sig_S});
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bool inv_s = cell->hasParam(ID(IS_S_INVERTED)) && cell->getParam(ID(IS_S_INVERTED)).as_bool();
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bool inv_s = cell->getParam(ID(IS_S_INVERTED)).as_bool();
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auto it_S = bit_to_lut.find(sig_S);
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if (it_S != bit_to_lut.end())
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lut_s = it_S->second.first;
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@ -271,7 +271,7 @@ lut_sigin_done:
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if (has_r) {
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SigBit sig_R = sigmap(cell->getPort(ID::R));
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LutData lut_r = LutData(Const(2, 2), {sig_R});
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bool inv_r = cell->hasParam(ID(IS_R_INVERTED)) && cell->getParam(ID(IS_R_INVERTED)).as_bool();
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bool inv_r = cell->getParam(ID(IS_R_INVERTED)).as_bool();
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auto it_R = bit_to_lut.find(sig_R);
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if (it_R != bit_to_lut.end())
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lut_r = it_R->second.first;
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