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Author	SHA1	Message	Date
Eddie Hung	0c3ed73dad	Count $_NOT_ cells turned into $luts	2019-07-11 09:55:14 -07:00
Eddie Hung	33862d0445	WIP for fixing partitioning, temporarily do not partition	2019-07-11 09:22:52 -07:00
Eddie Hung	c0abd18799	Enable &mfs for abc9, even if it only currently works for ice40	2019-07-11 08:49:06 -07:00
Marcin Kościelnicki	ce250b341c	synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 14:45:48 +02:00
Eddie Hung	d357431df1	Restore from master	2019-07-10 22:54:39 -07:00
Eddie Hung	f984e0cb34	Another typo	2019-07-10 22:33:35 -07:00
Clifford Wolf	9112850800	Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark ... write_verilog: write RTLIL::Sa aka - as Verilog ?	2019-07-11 07:25:52 +02:00
Clifford Wolf	fd3d5cefad	Merge pull request #1179 from whitequark/attrmap-proc ... attrmap: also consider process, switch and case attributes	2019-07-11 07:23:28 +02:00
Eddie Hung	375fcbe511	abc_flop to also get topologically sorted	2019-07-10 20:26:09 -07:00
Eddie Hung	9f608d6be3	write_verilog with *.v extension	2019-07-10 20:25:59 -07:00
Eddie Hung	ea6ffea2cd	Fix clk_pol for FD*_1	2019-07-10 20:10:20 -07:00
Eddie Hung	7899a06ed6	Another typo	2019-07-10 19:59:24 -07:00
Eddie Hung	ad35b509de	Another typo	2019-07-10 19:05:53 -07:00
Eddie Hung	e603d719d6	Fix spacing	2019-07-10 19:04:22 -07:00
Eddie Hung	f3511e4f93	Use \$currQ	2019-07-10 19:01:13 -07:00
Eddie Hung	71acd3ddcf	Remove -retime from abc9, revert to abc behav with separate clock/en domains	2019-07-10 18:57:44 -07:00
Eddie Hung	f030be3f1c	Preserve all parameters, plus some extra ones for clk/en polarity	2019-07-10 18:57:11 -07:00
Eddie Hung	f8f0ffe786	Small opt	2019-07-10 18:56:50 -07:00
Eddie Hung	4a995c5d80	Change how to specify flops to ABC again	2019-07-10 17:54:56 -07:00
Eddie Hung	a092c48f03	Use split_tokens()	2019-07-10 17:34:51 -07:00
Eddie Hung	3bb48facb2	Remove params from FD*_1 variants	2019-07-10 17:17:54 -07:00
Eddie Hung	0372c900e8	Fix typo, and have !{PRE,CLR} behave as CE	2019-07-10 17:15:49 -07:00
Eddie Hung	7b2599cb94	Move ABC FF stuff to abc_ff.v; add support for other FD* types	2019-07-10 17:06:05 -07:00
Eddie Hung	0ab8f28bc7	Uncomment IS_C_INVERTED parameter	2019-07-10 16:23:15 -07:00
Eddie Hung	838ae1a14c	synth_xilinx's map_cells stage to techmap ff_map.v	2019-07-10 16:15:57 -07:00
Eddie Hung	73c8f1a59e	Fix box numbering	2019-07-10 16:12:33 -07:00
Eddie Hung	052060f109	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-07-10 16:05:41 -07:00
Eddie Hung	b33ecd2a74	Move dsp_map.v into cells_map.v; cleanup synth_xilinx a little	2019-07-10 16:00:03 -07:00
Eddie Hung	cea7441d8a	Merge remote-tracking branch 'origin/master' into xc7dsp	2019-07-10 15:58:01 -07:00
Eddie Hung	bb2144ae73	Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime ... Error out if -abc9 and -retime specified	2019-07-10 14:38:13 -07:00
Eddie Hung	2f990a7319	Merge pull request #1148 from YosysHQ/xc7mux ... synth_xilinx to infer wide multiplexers using new '-widemux <min>' option	2019-07-10 14:38:00 -07:00
Eddie Hung	6bbd286e03	Error out if -abc9 and -retime specified	2019-07-10 12:47:48 -07:00
Eddie Hung	58bb84e5b2	Add some spacing	2019-07-10 12:32:33 -07:00
Eddie Hung	521971e32e	Add some ASCII art explaining mux decomposition	2019-07-10 12:20:04 -07:00
whitequark	ea447220da	attrmap: also consider process, switch and case attributes.	2019-07-10 12:30:53 +00:00
Clifford Wolf	c66b4b9131	Merge pull request #1177 from YosysHQ/clifford/async ... Fix clk2fflogic adff reset semantic to negative hold time on reset	2019-07-10 08:48:20 +02:00
Eddie Hung	e573d024a2	Call muxpack and pmux2shiftx before cmp2lut	2019-07-09 21:26:38 -07:00
Eddie Hung	1122a2e067	Fix first divergence in #1178	2019-07-09 15:49:16 -07:00
Eddie Hung	c55530b901	Restore opt_clean back to original place	2019-07-09 14:29:58 -07:00
Eddie Hung	5b48b18d29	Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6	2019-07-09 14:28:54 -07:00
David Shah	27b27b8781	synth_ecp5: Fix typo in copyright header ... Signed-off-by: David Shah <dave@ds0.me>	2019-07-09 22:26:10 +01:00
Clifford Wolf	1d58bbb79c	Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position ... write_verilog: fix placement of case attributes	2019-07-09 22:19:34 +01:00
Clifford Wolf	cae26bf330	Merge pull request #1174 from YosysHQ/eddie/fix1173 ... Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero	2019-07-09 22:59:51 +02:00
Clifford Wolf	6dd33be7ce	Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position ... write_verilog: fix placement of case attributes	2019-07-09 22:51:25 +02:00
Clifford Wolf	9546ccdbd3	Fix tests/various/async FFL test ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-07-09 22:44:39 +02:00
Clifford Wolf	5138621482	Improve tests/various/async, disable failing ffl test ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-07-09 22:21:25 +02:00
Eddie Hung	b1a048a703	Extend using A[1] to preserve don't care	2019-07-09 12:35:41 -07:00
Eddie Hung	f604aa174e	Merge pull request #1171 from YosysHQ/revert-1166-eddie/synth_keepdc ... Revert "Add "synth -keepdc" option"	2019-07-09 12:19:40 -07:00
Eddie Hung	bee5d2b21a	Merge remote-tracking branch 'origin/eddie/fix1173' into xc7mux	2019-07-09 12:16:33 -07:00
whitequark	37bb6b5e96	write_verilog: fix placement of case attributes. NFC.	2019-07-09 19:14:03 +00:00