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Small opt
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@ -749,7 +749,6 @@ void AigerReader::post_process()
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log_assert(box_module);
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RTLIL::Module* flop_module = nullptr;
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const RTLIL::IdString flop_past_q = RTLIL::escape_id("\\$pastQ");
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if (seen_boxes.insert(cell->type).second) {
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auto it = box_module->attributes.find("\\abc_flop");
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if (it != box_module->attributes.end()) {
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@ -830,7 +829,7 @@ void AigerReader::post_process()
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rhs.append(wire);
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}
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if (!flop_module || port_name != flop_past_q)
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if (!flop_module || port_name != "\\$pastQ")
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cell->setPort(port_name, rhs);
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}
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