2170 commits

Author	SHA1	Message	Date
Emil J. Tywoniak	7652b1b52e	opt_expr: WIP use patcher more	2026-07-17 23:48:18 +02:00
Emil J. Tywoniak	900649282f	patch: cleanup	2026-07-17 23:48:12 +02:00
Emil J. Tywoniak	c7467e7edd	patch: infer leaves for gc	2026-07-17 23:48:12 +02:00
Emil J. Tywoniak	19d007cd65	patch: instead of cell->cell, use port->sig rewrites	2026-07-17 23:48:12 +02:00
Emil J. Tywoniak	169445f54a	patch: fix gc	2026-07-17 23:48:06 +02:00
Emil J. Tywoniak	d01b9816b3	patch: fix const handling	2026-07-17 23:48:06 +02:00
Emil J. Tywoniak	c7a8fe1c79	rtlil, patch: update signorm index and driver fields when committing Cell from Patch to Design	2026-07-17 23:48:06 +02:00
Emil J. Tywoniak	b95565a8d9	fixup! patch: working multi-cell signorm invariant	2026-07-17 23:48:06 +02:00
Emil J. Tywoniak	07d5115135	patch: source transfer	2026-07-17 23:48:06 +02:00
Emil J. Tywoniak	71f7f586aa	patch: working multi-cell signorm invariant	2026-07-17 23:48:06 +02:00
Emil J. Tywoniak	e331300c58	patch: fix patch mixins	2026-07-17 23:48:00 +02:00
Emil J. Tywoniak	2c1d114cb1	patch: WIP multicell patch test	2026-07-17 23:48:00 +02:00
Emil J. Tywoniak	8818cade7a	patch: wires	2026-07-17 23:48:00 +02:00
Emil J. Tywoniak	9f0c1843d3	patch: signorm, move	2026-07-17 23:48:00 +02:00
Emil J. Tywoniak	a00631595f	patch: unique heap	2026-07-17 23:48:00 +02:00
Emil J. Tywoniak	277b6f47dc	rtlil: add CellAdderMixin for shared Cell adder interface between Module and Patch	2026-07-17 23:48:00 +02:00
Emil J. Tywoniak	fc07fd9332	patch: GC comment	2026-07-17 23:47:35 +02:00
Emil J. Tywoniak	240dda9186	test_patch total basics	2026-07-17 23:47:35 +02:00
Emil J. Tywoniak	62cd00aeeb	rtlil: allow friends to use Wire constructors with a factory token pattern	2026-07-17 23:47:08 +02:00
Emil J. Tywoniak	20b0a9934b	rtlil: allow friends to use Cell constructors with a factory token pattern	2026-07-17 23:47:08 +02:00
Emil J. Tywoniak	77dd01edfc	patcher: start	2026-07-17 23:47:08 +02:00
Emil J. Tywoniak	abebf4f2db	signorm: safer indexing if broken invariant	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	f2e5bcb86a	rtlil: publish signorm fanout	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	3010c0fc31	signorm: add timers	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	fb06c1add5	rtlil_bufnorm: fix setup_driven_wires constant handling on unknown port direction	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	83fa720157	rtlil_bufnorm: more xlog	2026-07-17 23:33:03 +02:00
Emil J. Tywoniak	360527af1a	rtlil: fix cloneInto in signorm	2026-07-17 23:33:03 +02:00
Emil J. Tywoniak	2fc93aa711	rtlil: sigNormalize Module when added to Design in signorm mode	2026-07-17 23:33:03 +02:00
Emil J. Tywoniak	f7149450b4	rtlil_bufnorm: more xlog	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	c40974ee59	rtlil_bufnorm: ignore timing info harder	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	8bcec792e2	ffmerge: initvals signorm compatibility fixup	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	3b1e79d312	timinginfo: special-case $specify2 in signorm invariant	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	aeaf095be4	ff: add FfDataSigMapped	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	9cc0997658	signorm: remove $input cells when leaving	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	c8faf605f7	signorm: skip const when fixing fanout	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	f6ed20664f	satgen: support $connect	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	b408a059ad	rtlil: add dump_sigmap for hacky signorm debugging	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	9521b22907	timinginfo: disable output wire check due to signorm	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	a7b62c6bc3	rtlil: forbid rewrite_sigspecs in signorm	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	d50f9b7bb1	ff: fixup initvals with signorm direct drive wire if it's created, not old driven wire	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	3b956cea1b	rtlil: fix zero width SigSpec crash in signorm setPort unsetPort	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	479ab70890	rtlil_bufnorm: fix cell deletion deferral bug	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	d93ab0d07f	mem: fix signorm cell type morph	2026-07-17 23:32:34 +02:00
Jannis Harder	b84beb598f	WIP half broken snapshot	2026-07-17 23:32:20 +02:00
Jannis Harder	51fc03688a	WIP remove dead code	2026-07-17 23:31:11 +02:00
nella	dddf137888	Merge pull request #6024 from YosysHQ/nella/scl-build-date ... Include build datetime in scl cache hash	2026-07-13 11:54:45 +00:00
nella	b678c238e4	Include build datetime in scl cache hash.	2026-07-10 12:44:34 +02:00
Michael Baier	58fc67ee66	Adding Width check to resize	2026-07-09 14:34:56 +02:00
Michael Baier	5cd9efefe3	Adding widht checks to backend	2026-07-09 14:34:56 +02:00
Michael Baier	ea41b196da	Adding Widht Limit	2026-07-09 14:34:56 +02:00