Marcin Kościelnicki
7562e7304e
xilinx: Use INV instead of LUT1 when applicable
2019-11-25 20:40:39 +01:00
Marcin Kościelnicki
7a9081440c
xilinx: Add simulation models for MULT18X18* and DSP48A*.
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This adds simulation models for the following primitives:
- MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3)
- MULT18X18SIO (Spartan 3E, Spartan 3A)
- DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1
- DSP48A1 (Spartan 6)
2019-11-19 01:00:58 +01:00
Marcin Kościelnicki
c4bd318e76
synth_xilinx: Merge blackbox primitive libraries.
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First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-06 15:11:27 +01:00
David Shah
3506eaf290
xilinx: Add URAM288 mapping for xcup
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-23 11:47:44 +01:00
David Shah
6769d31ddb
xilinx: Add support for UltraScale[+] BRAM mapping
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-23 11:47:37 +01:00
Marcin Kościelnicki
7b350cacd4
xilinx: Support multiplier mapping for all families.
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This supports several older families that are not yet supported for
actual logic synthesis — the intention is to add them soon.
2019-10-22 18:06:57 +02:00
Clifford Wolf
a3a7bb9bf7
Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg
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Call memory_dff before DSP mapping to reserve registers (fixes #1447 )
2019-10-22 17:36:54 +02:00
Sean Cross
82f60ba938
Makefile: don't assume python is called python3
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On some architectures, notably on Windows, the official name for the
Python binary from python.org is `python`. The build system assumes
that python is called `python3`, which breaks under this architecture.
There is already infrastructure in place to determine the name of the
Python binary when building PYOSYS. Since Python is now always required
to build Yosys, enable this check universally which sets the
`PYTHON_EXECUTABLE` variable.
Then, reuse this variable in other Makefiles as necessary, rather than
hardcoding `python3` everywhere.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-10-19 14:04:52 +08:00
N. Engelhardt
3b405d985e
Call memory_dff before DSP mapping to reserve registers ( fixes #1447 )
2019-10-17 21:33:54 +02:00
Marcin Kościelnicki
526fe4cb89
xilinx: Add simulation model for IBUFG.
2019-10-10 13:16:03 +02:00
Eddie Hung
9fd2ddb14c
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
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Rename abc_* names/attributes to more precisely be abc9_*
2019-10-08 10:53:38 -07:00
Eddie Hung
6c5e1234e1
Add comment on why partial multipliers are 18x18
2019-10-04 22:31:04 -07:00
Eddie Hung
b47bb5c810
Fix typo in check_label()
2019-10-04 21:43:50 -07:00
Eddie Hung
a5ac33f230
Merge branch 'master' into eddie/abc_to_abc9
2019-10-04 17:53:20 -07:00
Eddie Hung
0acc51c3d8
Add temporary abc9 -nomfs and use for synth_xilinx -abc9
2019-10-04 17:35:43 -07:00
Eddie Hung
9c23811839
Remove DSP48E1 from *_cells_xtra.v
2019-10-04 17:26:42 -07:00
Eddie Hung
aae2b9fd9c
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
Eddie Hung
5b5756b91e
Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
2019-09-30 12:52:43 +02:00
Marcin Kościelnicki
4535f2c694
synth_xilinx: Support latches, remove used-up FF init values.
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Fixes #1387 .
2019-09-30 12:52:43 +02:00
Eddie Hung
8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp
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DSP inference for Xilinx (improved for ice40, initial support for ecp5)
2019-09-29 11:26:22 -07:00
Eddie Hung
c372e7baf9
Fix box name
2019-09-27 18:49:45 -07:00
Eddie Hung
b3d8a60cbd
Re-order
2019-09-27 14:32:07 -07:00
Eddie Hung
143f82def2
Missing an '&'
2019-09-26 11:13:08 -07:00
Eddie Hung
033aefc0f4
Typo
2019-09-26 10:34:14 -07:00
Eddie Hung
781dda6175
select once
2019-09-26 10:15:05 -07:00
Eddie Hung
27e5bf5aad
Stop trying to be too smart by prematurely optimising
2019-09-26 09:57:11 -07:00
Eddie Hung
53ea5daa42
Call 'wreduce' after mul2dsp to avoid unextend()
2019-09-25 14:04:36 -07:00
Eddie Hung
93363c94a2
Oops. Actually use __NAME__ in ABC_DSP48E1 macro
2019-09-25 10:33:16 -07:00
Eddie Hung
b41d2fb4e4
Add (* techmap_autopurge *) to abc_unmap.v too
2019-09-23 22:02:22 -07:00
Eddie Hung
11ac37733d
Add techmap_autopurge to outputs in abc_map.v too
2019-09-23 21:56:28 -07:00
Eddie Hung
27167848f4
Revert "Add a xilinx_finalise pass"
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This reverts commit 23d90e0439
2019-09-23 19:52:55 -07:00
Eddie Hung
0f53893104
Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"
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This reverts commit 67c2db3486
2019-09-23 19:52:55 -07:00
Eddie Hung
29db96fa1f
Revert "Vivado does not like zero width port connections"
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This reverts commit 895e2befa7
2019-09-23 19:52:54 -07:00
Eddie Hung
895e2befa7
Vivado does not like zero width port connections
2019-09-23 19:04:07 -07:00
Eddie Hung
67c2db3486
Remove (* techmap_autopurge *) from abc_unmap.v since no effect
2019-09-23 18:56:18 -07:00
Eddie Hung
23d90e0439
Add a xilinx_finalise pass
2019-09-23 18:56:02 -07:00
Eddie Hung
4401e5f142
Grammar
2019-09-20 14:24:31 -07:00
Eddie Hung
289cf688b7
Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40
2019-09-20 09:02:29 -07:00
Eddie Hung
691686f92c
Tidy up, fix undriven
2019-09-19 20:04:52 -07:00
Eddie Hung
1602516a8b
$__ABC_REG to have WIDTH parameter
2019-09-19 19:37:45 -07:00
Eddie Hung
e09f80479e
Fix DSP48E1 timing by breaking P path if MREG or PREG
2019-09-19 18:59:28 -07:00
Eddie Hung
362a803779
Revert "Different approach to timing"
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This reverts commit 41256f48a5
2019-09-19 18:33:38 -07:00
Eddie Hung
41256f48a5
Different approach to timing
2019-09-19 18:33:29 -07:00
Eddie Hung
5ca25b0c59
Suppress $anyseq warnings
2019-09-19 16:27:14 -07:00
Eddie Hung
595fb611a5
Use (* techmap_autopurge *) to suppress techmap warnings
2019-09-19 15:58:01 -07:00
Eddie Hung
c15a35db84
D is 25 bits not 24 bits wide
2019-09-19 15:55:49 -07:00
Eddie Hung
b88f0f6450
Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp
2019-09-19 15:47:41 -07:00
Eddie Hung
95db2489bd
synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2
2019-09-19 14:58:06 -07:00
Marcin Kościelnicki
13fa873f11
Use extractinv for synth_xilinx -ise
2019-09-19 04:02:48 +02:00
Eddie Hung
fd3b033903
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-18 12:23:22 -07:00
