Udi Finkelstein
73d426bc87
Modified errors into warnings
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No longer false warnings for memories and assertions
2018-06-05 18:03:22 +03:00
Udi Finkelstein
2b9c75f8e3
This PR should be the base for discussion, do not merge it yet!
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It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements.
What it DOES'T do:
Detect registers connected to output ports of instances.
Where it FAILS:
memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals.
You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
2018-03-11 23:09:34 +02:00
Clifford Wolf
eb67a7532b
Add $allconst and $allseq cell types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
Clifford Wolf
a96c775a73
Add support for "yosys -E"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-07 16:36:13 +01:00
Clifford Wolf
34005348b6
Bugfix in verilog_defaults argument parser
2017-12-24 17:21:37 +01:00
Clifford Wolf
777f2881d8
Add Verilog "automatic" keyword (ignored in synthesis)
2017-11-23 08:51:38 +01:00
Clifford Wolf
5b6e52118c
Accept real-valued delay values
2017-11-18 10:01:30 +01:00
William D. Jones
abc5b4b8ce
Accommodate Windows-style paths during include-file processing.
2017-11-14 16:16:24 -05:00
Udi Finkelstein
72a08eca3d
Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textbook solution
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(Oreilly 'Flex & Bison' page 189)
2017-09-30 06:39:07 +03:00
Clifford Wolf
2c04d883b1
Minor coding style fix
2017-09-26 13:50:14 +02:00
Clifford Wolf
cb1d439d10
Merge branch 'master' of https://github.com/combinatorylogic/yosys into combinatorylogic-master
2017-09-26 13:48:13 +02:00
Clifford Wolf
2cc09161ff
Fix ignoring of simulation timings so that invalid module parameters cause syntax errors
2017-09-26 01:52:59 +02:00
combinatorylogic
64ca0be971
Adding support for string macros and macros with arguments after include
2017-09-21 18:25:02 +01:00
Clifford Wolf
26766da343
Add a paragraph about pre-defined macros to read_verilog help message
2017-07-21 14:34:53 +02:00
Clifford Wolf
8f8baccfde
Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg"
2017-06-07 12:30:24 +02:00
Clifford Wolf
129984e115
Fix handling of Verilog ~& and ~| operators
2017-06-01 12:43:21 +02:00
Clifford Wolf
e91548b33e
Add support for localparam in module header
2017-04-30 17:20:30 +02:00
Clifford Wolf
f0db8ffdbc
Add support for `resetall compiler directive
2017-04-26 16:09:41 +02:00
Clifford Wolf
088f9c9cab
Fix verilog pre-processor for multi-level relative includes
2017-03-14 17:30:20 +01:00
Clifford Wolf
5b3b5ffc8c
Allow $anyconst, etc. in non-formal SV mode
2017-03-01 10:47:05 +01:00
Clifford Wolf
5f1d0b1024
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
Clifford Wolf
00dba4c197
Add support for SystemVerilog unique, unique0, and priority case
2017-02-23 16:33:19 +01:00
Clifford Wolf
34d4e72132
Added SystemVerilog support for ++ and --
2017-02-23 11:21:33 +01:00
Clifford Wolf
848062088c
Add checker support to verilog front-end
2017-02-09 13:51:44 +01:00
Clifford Wolf
ef4a28e112
Add SV "rand" and "const rand" support
2017-02-08 14:38:15 +01:00
Clifford Wolf
6abf79eb28
Further improve cover() support
2017-02-04 17:02:13 +01:00
Clifford Wolf
3928482a3c
Add $cover cell type and SVA cover() support
2017-02-04 14:14:26 +01:00
Clifford Wolf
fea528280b
Add "enum" and "typedef" lexer support
2017-01-17 17:33:52 +01:00
Clifford Wolf
3886669ab6
Added "verilog_defines" command
2016-12-15 17:49:28 +01:00
Clifford Wolf
ecdc22b06c
Added support for macros as include file names
2016-11-28 14:50:17 +01:00
Clifford Wolf
c7f6fb6e17
Bugfix in "read_verilog -D NAME=VAL" handling
2016-11-28 14:45:05 +01:00
Clifford Wolf
70d7a02cae
Added support for hierarchical defparams
2016-11-15 13:35:19 +01:00
Clifford Wolf
a926a6afc2
Remember global declarations and defines accross read_verilog calls
2016-11-15 12:42:43 +01:00
Clifford Wolf
bdc316db50
Added $anyseq cell type
2016-10-14 15:24:03 +02:00
Clifford Wolf
6f41e5277d
Removed $aconst cell type
2016-08-30 19:09:56 +02:00
Clifford Wolf
eae390ae17
Removed $predict again
2016-08-28 21:35:33 +02:00
Clifford Wolf
1276c87a56
Added read_verilog -norestrict -assume-asserts
2016-08-26 23:35:27 +02:00
Clifford Wolf
4be4969bae
Improved verilog parser errors
2016-08-25 11:44:37 +02:00
Clifford Wolf
cd18235f30
Added SV "restrict" keyword
2016-08-24 15:30:08 +02:00
Clifford Wolf
7f755dec75
Fixed bug in parsing real constants
2016-08-06 13:16:23 +02:00
Clifford Wolf
4056312987
Added $anyconst and $aconst
2016-07-27 15:41:22 +02:00
Clifford Wolf
a7b0769623
Added "read_verilog -dump_rtlil"
2016-07-27 15:40:17 +02:00
Clifford Wolf
5b944ef11b
Fixed a verilog parser memory leak
2016-07-25 16:37:58 +02:00
Clifford Wolf
7a67add95d
Fixed parsing of empty positional cell ports
2016-07-25 12:48:03 +02:00
Clifford Wolf
9aae1d1e8f
No tristate warning message for "read_verilog -lib"
2016-07-23 11:56:53 +02:00
Clifford Wolf
5c166e76e5
Added $initstate cell type and vlog function
2016-07-21 14:23:22 +02:00
Clifford Wolf
d7763634b6
After reading the SV spec, using non-standard predict() instead of expect()
2016-07-21 13:34:33 +02:00
Clifford Wolf
721f1f5ecf
Added basic support for $expect cells
2016-07-13 16:56:17 +02:00
Ruben Undheim
545bcb37e8
Allow defining input ports as "input logic" in SystemVerilog
2016-06-20 20:16:37 +02:00
Ruben Undheim
178ff3e7f6
Added support for SystemVerilog packages with localparam definitions
2016-06-18 10:53:55 +02:00