3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-07 09:55:20 +00:00
yosys/frontends/verilog
Udi Finkelstein 73d426bc87 Modified errors into warnings
No longer false warnings for memories and assertions
2018-06-05 18:03:22 +03:00
..
.gitignore Updated .gitignore file for ilang and verilog frontends 2014-10-15 01:14:38 +02:00
const2ast.cc Fixed segfault on invalid verilog constant 1'b_ 2015-09-22 08:13:09 +02:00
Makefile.inc Adjust makefiles to work with out-of-tree builds 2015-08-12 15:04:44 +02:00
preproc.cc Add support for "yosys -E" 2018-01-07 16:36:13 +01:00
verilog_frontend.cc Bugfix in verilog_defaults argument parser 2017-12-24 17:21:37 +01:00
verilog_frontend.h Remember global declarations and defines accross read_verilog calls 2016-11-15 12:42:43 +01:00
verilog_lexer.l This PR should be the base for discussion, do not merge it yet! 2018-03-11 23:09:34 +02:00
verilog_parser.y Modified errors into warnings 2018-06-05 18:03:22 +03:00