Emil J. Tywoniak
fcdd013c57
quicklogic: allow fractured mode on canonical dspv1 modules
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
62885f1de3
quicklogic: ql_dsp_simd remove unused MODE_BITS packing
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
f55da95ec8
quicklogic: update dspv2_sim.v to v1.1 Feb21
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
9b52ba8738
quicklogic: ql_dsp_simd add dspv2 support, fix dspv1
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
ed239b69fd
ql_dsp_macc: whitespace. NFC
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
651d5728d0
ql_dsp_macc: dspv2
2025-03-11 10:35:30 +01:00
Emil J. Tywoniak
47b270a03e
synth_quicklogic: enable dspv2 tests, fix -dspv2
2025-03-11 10:35:30 +01:00
Emil J. Tywoniak
c451d8ebb9
synth_quicklogic: add -dspv2 to opt into v2 DSP blocks
2025-03-11 10:35:30 +01:00
Martin Povišer
e1074e0e4e
qlf_k6n10f: Fix DSPV2 models
2025-03-11 10:35:01 +01:00
Martin Povišer
531374bec1
qlf_k6n10f: New ql_dsp pass, move to DSPV2
2025-03-11 10:35:01 +01:00
Martin Povišer
9f7cdd4bd4
Merge pull request #4262 from RoaLogic/master
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MAX10 updates
2025-03-07 19:59:55 +01:00
N. Engelhardt
268a034b21
Merge pull request #4866 from YosysHQ/ql_ioff
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add IOFF inference for qlf_k6n10f
2025-03-03 14:12:09 +00:00
N. Engelhardt
303a386ecc
create duplicate IOFFs if multiple output ports are connected to the same register
2025-01-31 11:28:57 +01:00
Krystine Sherwin
0ec5f1b756
pmgen: Move passes out of pmgen folder
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- Techlib pmgens are now in relevant techlibs/*.
- `peepopt` pmgens are now in passes/opt.
- `test_pmgen` is still in passes/pmgen.
- Update `Makefile.inc` and `.gitignore` file(s) to match new `*_pm.h` location,
as well as the `#include`s.
- Change default `%_pm.h` make target to `techlibs/%_pm.h` and move it to the
top level Makefile.
- Update pmgen target to use `$(notdir $*)` (where `$*` is the part of the file
name that matched the '%' in the target) instead of `$(subst _pm.h,,$(notdir
$@))`.
2025-01-31 15:18:28 +13:00
N. Engelhardt
25b400982b
detect aliased I/O ports
2025-01-28 17:37:23 +01:00
N. Engelhardt
9da4fe747e
fix bus ioff inference
2025-01-28 11:23:36 +01:00
N. Engelhardt
1cf8e7c7db
add ioff inference for qlf_k6n10f
2025-01-24 21:17:15 +01:00
Emil J. Tywoniak
a58481e9b7
mark all hash_into methods nodiscard
2025-01-14 12:39:15 +01:00
Emil J
9f7040b3d1
Merge pull request #4683 from keszybz/use-SOURCE_DATE_EPOCH
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Respect $SOURCE_DATE_EPOCH in generate_bram_types_sim.py
2025-01-10 23:43:26 +01:00
Emil J. Tywoniak
b9b9515bb0
hashlib: hash_eat -> hash_into
2024-12-18 15:09:25 +01:00
Emil J. Tywoniak
4e29ec1854
hashlib: acc -> eat
2024-12-18 15:09:25 +01:00
Emil J. Tywoniak
d071489ab1
hashlib: redo interface for flexibility
2024-12-18 14:49:25 +01:00
Miodrag Milanović
f4ddbc3994
Merge pull request #4771 from pepijndevos/famxtra
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gowin: split cells_xtra by family
2024-12-08 19:46:36 +01:00
KrystalDelusion
c96d02b204
Merge pull request #4784 from YosysHQ/krys/reduce_warnings
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Reduce number of warnings
2024-12-05 09:16:06 +13:00
Emil J
61a6567b9f
Merge pull request #4789 from YosysHQ/emil/sklansky-adder
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Add a Sklansky option for `$lcu` mapping
2024-12-03 11:33:13 +01:00
Emil J. Tywoniak
fe64a714a9
techmap: add a Sklansky option for $lcu mapping
2024-12-02 11:34:58 +01:00
Emil J. Tywoniak
ebd7f2b366
techlibs: add _TECHMAP_DO_ to Han-Carlson adder
2024-12-02 09:54:24 +01:00
Krystine Sherwin
1de5d98ae2
Reduce comparisons of size_t and int
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`Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`.
For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.
2024-11-29 12:53:29 +13:00
Emil J. Tywoniak
4bf3677640
techmap: set Han-Carlson adder priority consistent with Kogge-Stone
2024-11-28 23:54:00 +01:00
Emil J. Tywoniak
6c78bd3637
techmap: add a Han-Carlson option for $lcu mapping
2024-11-28 15:33:21 +01:00
Pepijn de Vos
be836f4af3
gowin: split cells_xtra by family
2024-11-26 15:42:22 +01:00
Emil J
88abc4c20f
Merge pull request #4755 from pepijndevos/cells_xtra
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Gowin: add GW2A and GW5A cells
2024-11-20 13:32:30 +01:00
Pepijn de Vos
b8329df1d0
add GW2A and GW5A cells
2024-11-17 20:25:11 +01:00
Patrick Urban
77e1f748a5
gatemate: run simplemap after muxcover to prevent unmapped multiplexers
2024-11-15 09:49:49 +01:00
Zbigniew Jędrzejewski-Szmek
26a3478d8d
Drop timestamp in generate_bram_types_sim.py
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I'm working on build reproducibility of Fedora packages, and this patch fixes
an issue observed in test rebuilds: the timestamp was set to the actual time
of the build, making builds nonreproducible.
Other "Generated by" strings do not include a timestamp, so drop it here too.
2024-10-30 08:47:18 +01:00
Krystine Sherwin
27b8b4e81e
Docs: Fix missing groups
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$lut and $sop were missed in the rebase, and $buf is new to main since the last rebase.
2024-10-15 11:08:30 +13:00
Krystine Sherwin
1513366f21
Docs: Adding mux cell descriptions
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Also making ver2 cell descriptions consistently spaced.
2024-10-15 07:37:34 +13:00
Krystine Sherwin
dfe803b5c6
Docs: Comments from @jix
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- Unswap shift/shiftx
- Add brief overview to cell lib
- Clarify $div cell B input
- Clarify unary operators
- What is $modfloor
2024-10-15 07:37:20 +13:00
Krystine Sherwin
4d84d7e69f
simlib.v: Add x-output tag
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Also a few extra cell help texts.
2024-10-15 07:35:41 +13:00
Krystine Sherwin
ed92374263
simlib.v: Update case equality operators to v2
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Also tag as x-aware cells and add titles.
2024-10-15 07:35:41 +13:00
Krystine Sherwin
b1025dbaa6
cellhelp.py: Cells can have tags
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Tags are added to the list of properties when exporting to `cells.json`.
2024-10-15 07:35:41 +13:00
Krystine Sherwin
f70a66f5b3
Docs: Assert cell has group
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Explicitly assign $_TBUF_ to `gate_other` and remove catch if a cell has no group.
2024-10-15 07:35:40 +13:00
Krystine Sherwin
5c4f7b4deb
Docs: $eqx aka case equality
2024-10-15 07:35:40 +13:00
Krystine Sherwin
596d914ead
simcells: Apply group tags
2024-10-15 07:35:40 +13:00
Krystine Sherwin
78b9dbd4ea
Docs: Assign remaining word cells to groups
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Move todos to correct place.
Add todo for x-prop cells.
2024-10-15 07:35:40 +13:00
Krystine Sherwin
1374fc2e2b
cellref: Deprecate cell_library.rst
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Most of the word/coarse level cells have an assigned group and individual page.
The gate/fine level cells are all on one page.
Fix links to `cell_library.rst`.
2024-10-15 07:34:52 +13:00
Krystine Sherwin
04b0ae540d
cellref: Move default help message to register.cc
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Drop the default help message from rst while still displaying it on the command line.
Fix command line formatting for older style help messages.
2024-10-15 07:31:47 +13:00
Krystine Sherwin
c662529316
Docs: Move binary operators to cell appendix
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Add binary group tag to relevant cells.
Remove content from `cell_library.rst` that is already moved.
2024-10-15 07:31:47 +13:00
Krystine Sherwin
7c5b10fe50
cellref: Add json dump
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New `help -dump-cells-json <file>` to dump cells list.
Add 'group' field to SimHelper class/struct with defaults to gate_other and word_other depending on source (simcells or simlib).
Add 'unary' group to unary operator cells for testing (based on internal cell library docs page).
2024-10-15 07:25:27 +13:00
Krystine Sherwin
06e5e18371
simlib.v: Autolink referenced cells in alu
2024-10-15 07:23:45 +13:00
