cellref: Add json dump

New `help -dump-cells-json <file>` to dump cells list.
Add 'group' field to SimHelper class/struct with defaults to gate_other and word_other depending on source (simcells or simlib).
Add 'unary' group to unary operator cells for testing (based on internal cell library docs page).

techlibs/common/cellhelp.py

@@ -12,6 +12,7 @@ class SimHelper:
     source: str = ""
     desc: list[str]
     code: list[str]
+    group: str = ""
     ver: str = "1"
 
     def __init__(self) -> None:
@@ -19,7 +20,7 @@ class SimHelper:
     
     def __str__(self) -> str:
         printed_fields = [
-            "name", "title", "ports", "source", "desc", "code", "ver",
+            "name", "title", "ports", "source", "desc", "code", "group", "ver",
         ]
         # generate C++ struct
         val = f"cell_help[{json.dumps(self.name)}] = "
@@ -28,6 +29,7 @@ class SimHelper:
             field_val = getattr(self, field)
             if isinstance(field_val, list):
                 field_val = "\n".join(field_val)
+            field_val = field_val.strip()
             val += f'  {json.dumps(field_val)},\n'
         val += "};\n"
         return val
@@ -80,9 +82,23 @@ for line in fileinput.input():
         if simHelper.ver == "1" and short_filename == "simcells.v":
             # default simcells parsing
             simcells_reparse(simHelper)
+
+        # check help
         if not simHelper.desc:
-            # no help
             simHelper.desc.append("No help message for this cell type found.\n")
+        elif simHelper.ver == "1" and short_filename == "simlib.v" and simHelper.desc[1].startswith('    '):
+            simHelper.desc.pop(1)
+
+        # check group
+        if not simHelper.group:
+            if short_filename == 'simcells.v':
+                simHelper.group = "gate_"
+            elif short_filename == 'simlib.v':
+                simHelper.group = "word_"
+            simHelper.group += "other"
+
+        # dump
         print(simHelper)
+        # new
         simHelper = SimHelper()
 

techlibs/common/simlib.v

@@ -33,11 +33,10 @@
 
 // --------------------------------------------------------
 
-//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-//-
-//-     $not (A, Y)
-//-
-//- A bit-wise inverter. This corresponds to the Verilog unary prefix '~' operator.
+//* ver 2
+//* title Bit-wise inverter
+//* group unary
+//- This corresponds to the Verilog unary prefix '~' operator.
 //-
 module \$not (A, Y);
 
@@ -63,6 +62,7 @@ endmodule
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
 //-     $pos (A, Y)
+//* group unary
 //-
 //- A buffer. This corresponds to the Verilog unary prefix '+' operator.
 //-
@@ -111,6 +111,7 @@ endmodule
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
 //-     $neg (A, Y)
+//* group unary
 //-
 //- An arithmetic inverter. This corresponds to the Verilog unary prefix '-' operator.
 //-
@@ -258,6 +259,7 @@ endmodule
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
 //-     $reduce_and (A, Y)
+//* group unary
 //-
 //- An AND reduction. This corresponds to the Verilog unary prefix '&' operator.
 //-
@@ -285,6 +287,7 @@ endmodule
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
 //-     $reduce_or (A, Y)
+//* group unary
 //-
 //- An OR reduction. This corresponds to the Verilog unary prefix '|' operator.
 //-
@@ -312,6 +315,7 @@ endmodule
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
 //-     $reduce_xor (A, Y)
+//* group unary
 //-
 //- A XOR reduction. This corresponds to the Verilog unary prefix '^' operator.
 //-
@@ -339,6 +343,7 @@ endmodule
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
 //-     $reduce_xnor (A, Y)
+//* group unary
 //-
 //- A XNOR reduction. This corresponds to the Verilog unary prefix '~^' operator.
 //-
@@ -366,6 +371,7 @@ endmodule
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
 //-     $reduce_bool (A, Y)
+//* group unary
 //-
 //- An OR reduction. This cell type is used instead of $reduce_or when a signal is
 //- implicitly converted to a boolean signal, e.g. for operands of '&&' and '||'.
@@ -1359,6 +1365,7 @@ endmodule
 //-
 //- A logical inverter. This corresponds to the Verilog unary prefix '!' operator.
 //-
+//* group unary
 module \$logic_not (A, Y);
 
 parameter A_SIGNED = 0;