289 commits

Author	SHA1	Message	Date
Clifford Wolf	ef4a28e112	Add SV "rand" and "const rand" support	2017-02-08 14:38:15 +01:00
Clifford Wolf	6abf79eb28	Further improve cover() support	2017-02-04 17:02:13 +01:00
Clifford Wolf	3928482a3c	Add $cover cell type and SVA cover() support	2017-02-04 14:14:26 +01:00
Clifford Wolf	fea528280b	Add "enum" and "typedef" lexer support	2017-01-17 17:33:52 +01:00
Clifford Wolf	70d7a02cae	Added support for hierarchical defparams	2016-11-15 13:35:19 +01:00
Clifford Wolf	bdc316db50	Added $anyseq cell type	2016-10-14 15:24:03 +02:00
Clifford Wolf	6f41e5277d	Removed $aconst cell type	2016-08-30 19:09:56 +02:00
Clifford Wolf	eae390ae17	Removed $predict again	2016-08-28 21:35:33 +02:00
Clifford Wolf	1276c87a56	Added read_verilog -norestrict -assume-asserts	2016-08-26 23:35:27 +02:00
Clifford Wolf	4be4969bae	Improved verilog parser errors	2016-08-25 11:44:37 +02:00
Clifford Wolf	7f755dec75	Fixed bug in parsing real constants	2016-08-06 13:16:23 +02:00
Clifford Wolf	4056312987	Added $anyconst and $aconst	2016-07-27 15:41:22 +02:00
Clifford Wolf	5b944ef11b	Fixed a verilog parser memory leak	2016-07-25 16:37:58 +02:00
Clifford Wolf	7a67add95d	Fixed parsing of empty positional cell ports	2016-07-25 12:48:03 +02:00
Clifford Wolf	9aae1d1e8f	No tristate warning message for "read_verilog -lib"	2016-07-23 11:56:53 +02:00
Clifford Wolf	5c166e76e5	Added $initstate cell type and vlog function	2016-07-21 14:23:22 +02:00
Clifford Wolf	d7763634b6	After reading the SV spec, using non-standard predict() instead of expect()	2016-07-21 13:34:33 +02:00
Clifford Wolf	721f1f5ecf	Added basic support for $expect cells	2016-07-13 16:56:17 +02:00
Ruben Undheim	545bcb37e8	Allow defining input ports as "input logic" in SystemVerilog	2016-06-20 20:16:37 +02:00
Ruben Undheim	178ff3e7f6	Added support for SystemVerilog packages with localparam definitions	2016-06-18 10:53:55 +02:00
Clifford Wolf	5a09fa4553	Fixed handling of parameters and const functions in casex/casez pattern	2016-04-21 15:31:54 +02:00
Clifford Wolf	33c10350b2	Fixed Verilog parser fix and more similar improvements	2016-03-15 12:22:31 +01:00
Andrew Becker	81d4e9e7c1	Use left-recursive rule for cell_port_list in Verilog parser.	2016-03-15 12:03:40 +01:00
Clifford Wolf	34f2b84fb6	Fixed handling of parameters and localparams in functions	2015-11-11 10:54:35 +01:00
Clifford Wolf	5308c1e02a	Fixed bug in verilog parser	2015-10-15 15:19:23 +02:00
Clifford Wolf	ba4cce9f19	Added support for "parameter" and "localparam" in global context	2015-10-07 14:59:08 +02:00
Clifford Wolf	a3a13cce32	Fixed detection of "task foo(bar);" syntax error	2015-09-22 21:34:21 +02:00
Clifford Wolf	e4ef000b70	Adjust makefiles to work with out-of-tree builds ... This is based on work done by Larry Doolittle	2015-08-12 15:04:44 +02:00
Clifford Wolf	6c84341f22	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
Clifford Wolf	1f1deda888	Added non-std verilog assume() statement	2015-02-26 18:47:39 +01:00
Clifford Wolf	dc1a0f06fc	Parser support for complex delay expressions	2015-02-20 10:21:36 +01:00
Clifford Wolf	e0e6d130cd	YosysJS stuff	2015-02-19 13:36:54 +01:00
Clifford Wolf	4f68a77e3f	Improved read_verilog support for empty behavioral statements	2015-02-10 12:17:29 +01:00
Clifford Wolf	1282a113da	Fixed supply0/supply1 with many wires	2014-12-11 13:56:20 +01:00
Clifford Wolf	87333f3ae2	Added warning for use of 'z' constants in HDL	2014-11-14 19:59:50 +01:00
Clifford Wolf	4e5350b409	Fixed parsing of nested verilog concatenation and replicate	2014-11-12 19:10:35 +01:00
Clifford Wolf	a21481b338	Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."	2014-10-30 14:01:02 +01:00
Clifford Wolf	f9c096eeda	Added support for task and function args in parentheses	2014-10-27 13:21:57 +01:00
William Speirs	fad0b0c506	Updated lexers & parsers to include prefixes	2014-10-15 00:48:19 +02:00

Renamed from frontends/verilog/parser.y (Browse further)