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6523 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Eddie Hung
c314ca3c51 Add test 2019-06-10 16:16:26 -07:00
Eddie Hung
b77c5da769 Revert "Revert "Move ff_map back after ABC for shregmap"" 
This reverts commit e473e74565.
 2019-06-10 14:37:09 -07:00
Eddie Hung
a1d4ae78a0 Revert "Rename shregmap -tech xilinx -> xilinx_dynamic" 
This reverts commit 94a5f4e609.
 2019-06-10 14:34:43 -07:00
Eddie Hung
7d27e1e431 Revert "shregmap -tech xilinx_dynamic to work -params and -enpol" 
This reverts commit 45d1bdf83a.
 2019-06-10 14:34:16 -07:00
Eddie Hung
3579d68193 Revert "Refactor to ShregmapTechXilinx7Static" 
This reverts commit e1e37db860.
 2019-06-10 14:34:15 -07:00
Eddie Hung
b6a39351f4 Revert "Add -tech xilinx_static" 
This reverts commit dfe9d95579.
 2019-06-10 14:34:14 -07:00
Eddie Hung
e1dbeb3004 Revert "Continue support for ShregmapTechXilinx7Static" 
This reverts commit 72eda94a66.
 2019-06-10 14:34:14 -07:00
Eddie Hung
9d8563178e Revert "shregmap -tech xilinx_static to handle INIT" 
This reverts commit 935df3569b.
 2019-06-10 14:34:12 -07:00
Bogdan Vukobratovic
d097f423d1 Refactor driver map generation 
- Implement iterators over the driver map that enumerate signals and cells
  within the cones of the signal
 2019-06-10 21:42:35 +02:00
Eddie Hung
352c532bb2 Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-10 11:02:54 -07:00
Eddie Hung
5b999ae68d Elaborate muxpack doc 2019-06-10 10:32:19 -07:00
Eddie Hung
1dd7e23a20 Merge remote-tracking branch 'origin/master' into eddie/muxpack 2019-06-10 10:28:40 -07:00
Eddie Hung
a91ea6612a Add some more comments 2019-06-10 10:27:55 -07:00
David Shah
498c21e735
Merge pull request #1082 from corecode/u4k 
ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k
 2019-06-10 15:12:23 +01:00
Simon Schubert
abf90b0403 ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k 2019-06-10 11:49:08 +02:00
Clifford Wolf
5a5cbf6458
Merge pull request #1078 from YosysHQ/eddie/muxcover_costs 
Allow muxcover costs to be changed
 2019-06-08 11:31:19 +02:00
Eddie Hung
d5f0b73fd9 Update CHANGELOG 2019-06-07 17:00:36 -07:00
Eddie Hung
816b5f5891 Comment out muxpack (currently broken) 2019-06-07 16:58:57 -07:00
Eddie Hung
5a46a0b385 Fine tune aigerparse 2019-06-07 16:57:32 -07:00
Eddie Hung
1e201a9b01 Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-07 16:15:19 -07:00
Eddie Hung
58f4b106f3 Merge branch 'master' into eddie/muxpack 2019-06-07 15:47:28 -07:00
Eddie Hung
2b350401c4 Fix spacing from spaces to tabs 2019-06-07 15:44:57 -07:00
Eddie Hung
f705f6a0b5 Comment O(N) -> O(N^2) 2019-06-07 15:39:12 -07:00
Eddie Hung
b959bf79c0 Add nonexcl case test, comment out two others 2019-06-07 15:35:15 -07:00
Eddie Hung
ba52d9b471 Extend ExclusiveDatabase to query SigSpec-s (for $pmux) 2019-06-07 15:34:16 -07:00
Eddie Hung
9b408838f1 Add ExclusiveDatabase to check exclusive $eq/$logic_not cell results 2019-06-07 14:18:17 -07:00
Clifford Wolf
7395a80690
Merge pull request #1079 from YosysHQ/eddie/fix_read_aiger 
Fix read_aiger to really get tested, and fix some uncovered read_aiger issues
 2019-06-07 23:13:34 +02:00
Eddie Hung
f48c6920b7 Add read_aiger to CHANGELOG 2019-06-07 13:12:48 -07:00
Eddie Hung
1da12c5071 Add @cliffordwolf freduce testcase 2019-06-07 12:12:11 -07:00
Eddie Hung
e263bc249b Add nonexclusive test from @cliffordwolf 2019-06-07 11:54:29 -07:00
Eddie Hung
887df8914c Resolve @cliffordwolf comment on redundant check 2019-06-07 11:37:52 -07:00
Eddie Hung
5ab59cd59e Resolve @cliffordwolf comment on sigmap 2019-06-07 11:36:19 -07:00
Eddie Hung
6934f4bdd5 Fix spacing (entire file is wrong anyway, will fix later) 2019-06-07 11:30:36 -07:00
Eddie Hung
d00ae1d6a8 Remove unnecessary std::getline() for ASCII 2019-06-07 11:28:25 -07:00
Eddie Hung
65924fd12f Test *.aag too, by using *.aig as reference 2019-06-07 11:28:05 -07:00
Eddie Hung
a04521c6b7 Fix read_aiger -- create zero driver, fix init width, parse 'b' 2019-06-07 11:07:15 -07:00
Eddie Hung
abc40924ed Use ABC to convert from AIGER to Verilog 2019-06-07 11:06:57 -07:00
Eddie Hung
ebe29b6659 Use ABC to convert AIGER to Verilog, then sat against Yosys 2019-06-07 11:05:36 -07:00
Eddie Hung
1b113a0574 Add symbols to AIGER test inputs for ABC 2019-06-07 11:05:25 -07:00
Eddie Hung
0f6e914ef6 Another muxpack test 2019-06-07 08:34:58 -07:00
Eddie Hung
30abdaf3b2 Allow muxcover costs to be changed 2019-06-07 08:34:11 -07:00
Eddie Hung
fe4394fb9a Allow muxcover costs to be changed 2019-06-07 08:30:39 -07:00
Clifford Wolf
6d49145497
Merge pull request #1077 from YosysHQ/clifford/pr983 
elaboration system tasks
 2019-06-07 13:39:46 +02:00
Clifford Wolf
f01a61f093 Rename implicit_ports.sv test to implicit_ports.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-07 13:12:25 +02:00
Clifford Wolf
211d85cfcc Fixes and cleanups in AST_TECALL handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-07 12:41:09 +02:00
Clifford Wolf
a3bbc5365b Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983 2019-06-07 12:08:42 +02:00
Clifford Wolf
169de05f3b Merge branch 'tux3-implicit_named_connection' 2019-06-07 11:53:46 +02:00
Clifford Wolf
7116621d22
Merge pull request #1076 from thasti/centos7-build-fix 
Fix pyosys-build on CentOS7
 2019-06-07 11:48:33 +02:00
Clifford Wolf
a0b57f2a6f Cleanup tux3-implicit_named_connection 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-07 11:46:16 +02:00
Clifford Wolf
b637b3109d Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys into tux3-implicit_named_connection 2019-06-07 11:41:54 +02:00