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Author	SHA1	Message	Date
Clifford Wolf	1979e0b1f2	Yosys 0.9 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-26 10:37:53 +02:00
Clifford Wolf	a3de83ef4a	Merge pull request #1112 from acw1251/pyosys_sigsig_issue ... Fixed pyosys commands returning RTLIL::SigSig	2019-08-25 11:22:02 +02:00
Eddie Hung	dc87372a97	Wire with init on FF part, 1'bx on non-FF part	2019-08-24 15:05:44 -07:00
Clifford Wolf	dc9c47b5af	Merge pull request #1327 from YosysHQ/clifford/pmgen ... Add pmgen slices and choices	2019-08-24 08:38:49 +02:00
Eddie Hung	7911143827	Create new $__XILINX_SHREG_ cell for variable length too	2019-08-23 18:15:49 -07:00
Eddie Hung	a048fc93e8	Do not allow Q of last cell of variable length SRL to be (* keep *)	2019-08-23 18:15:24 -07:00
Eddie Hung	ee9f6e6243	Also add first.Q to chain_bits since variable length	2019-08-23 18:14:06 -07:00
Eddie Hung	70ce3d0670	Do not enforce !EN_POLARITY on $dffe	2019-08-23 18:11:28 -07:00
Eddie Hung	188b49378a	Create new cell for fixed length SRL	2019-08-23 17:25:30 -07:00
Eddie Hung	e081303ee8	Cleanup FDRE matching	2019-08-23 17:23:52 -07:00
Eddie Hung	d7051b90de	Add undocumented feature	2019-08-23 16:41:32 -07:00
Eddie Hung	54488cfb82	Oops don't need a finally block	2019-08-23 16:39:37 -07:00
Eddie Hung	83e2d87fb8	Keep track of bits in variable length chain, to check for taps	2019-08-23 16:21:10 -07:00
Eddie Hung	f2d4814284	Don't forget $dff has no EN	2019-08-23 16:14:57 -07:00
Eddie Hung	2217d926a9	Same for variable length	2019-08-23 16:13:16 -07:00
Eddie Hung	b1caf7be5e	Filter on en_port for fixed length	2019-08-23 16:09:46 -07:00
Eddie Hung	513af10d77	Check clock is consistent	2019-08-23 15:18:26 -07:00
Eddie Hung	c762618783	Fix last_cell.D	2019-08-23 15:08:49 -07:00
Eddie Hung	ca5de78e76	Revert "Add a unique argument to pmgen's nusers()" ... This reverts commit 1d88887cfd.	2019-08-23 15:04:00 -07:00
Eddie Hung	e85e6e8d45	Revert "Fix polarity" ... This reverts commit 9cd23cf0fe.	2019-08-23 15:03:42 -07:00
Eddie Hung	9cd23cf0fe	Fix polarity	2019-08-23 14:49:34 -07:00
Eddie Hung	c2757613b6	Check for non unique nusers/fanouts	2019-08-23 14:32:36 -07:00
Eddie Hung	1d88887cfd	Add a unique argument to pmgen's nusers()	2019-08-23 14:32:17 -07:00
Eddie Hung	8ecfd55d5a	Update doc	2019-08-23 14:16:41 -07:00
Eddie Hung	3d7f4aa0c8	Remove (* init *) entry when consumed into SRL	2019-08-23 13:56:01 -07:00
Eddie Hung	3fa826254f	Merge branch 'xaig_arrival' of github.com:YosysHQ/yosys into xaig_arrival	2019-08-23 13:46:17 -07:00
Eddie Hung	48c424e45b	Cleanup	2019-08-23 13:46:05 -07:00
Eddie Hung	3c1c376fb1	Revert to upstream	2019-08-23 13:22:37 -07:00
Eddie Hung	455da57272	Fix spacing	2019-08-23 13:21:21 -07:00
Eddie Hung	85d39653ac	Remove unused model	2019-08-23 13:20:29 -07:00
Eddie Hung	967a36c125	indo -> into	2019-08-23 13:16:50 -07:00
Eddie Hung	a1f78eab04	indo -> into	2019-08-23 13:15:41 -07:00
Eddie Hung	5939ffdc07	Forgot to slice	2019-08-23 13:06:59 -07:00
Eddie Hung	242b3083ea	Cope with possibility that D could connect to Q on same cell	2019-08-23 13:06:31 -07:00
Eddie Hung	4a4e28b55e	Revert earliest to gcc-4.8, compile iverilog with default compiler	2019-08-23 12:29:57 -07:00
Eddie Hung	b3dc28cf65	Revert "Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!" ... This reverts commit c82b2fa31f.	2019-08-23 12:29:57 -07:00
Eddie Hung	fcb102d60e	Remove .0 from clang-8.0	2019-08-23 12:29:57 -07:00
Eddie Hung	fdc438e551	Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!	2019-08-23 12:29:57 -07:00
Eddie Hung	bf40f2f895	bionic -> xenial as its on whitelist	2019-08-23 12:29:57 -07:00
Eddie Hung	43927e5910	Bump gcc from 4.8 to 4.9 as undefined reference ... ... to `__warn_memset_zero_len'. Also remove gcc-6, bump gcc-7 to gcc-9, clang from 5.0 to 8.0	2019-08-23 12:29:50 -07:00
Eddie Hung	cee30deef5	Mention shregmap -tech xilinx is superseded	2019-08-23 12:24:25 -07:00
Eddie Hung	08139aa53a	xilinx_srl now copes with word-level flops $dff{,e}	2019-08-23 12:22:46 -07:00
Eddie Hung	18b64609c2	xilinx_srl to use 'slice' features of pmgen for word level	2019-08-23 12:22:06 -07:00
Eddie Hung	f4fd41d5d2	Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl	2019-08-23 11:35:06 -07:00
Eddie Hung	78b7d8f531	Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl	2019-08-23 11:32:44 -07:00
Eddie Hung	e658d472c8	Put attributes above port	2019-08-23 11:31:20 -07:00
Eddie Hung	d672b1ddec	Merge remote-tracking branch 'origin/master' into xaig_arrival	2019-08-23 11:26:55 -07:00
Eddie Hung	20f4d191b5	Merge branch 'master' into mwk/xilinx_bufgmap	2019-08-23 11:24:19 -07:00
Eddie Hung	509c353fe9	Forgot one	2019-08-23 11:23:50 -07:00
Eddie Hung	0d0ad15898	Merge branch 'master' into mwk/xilinx_bufgmap	2019-08-23 11:23:31 -07:00