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17693 commits 143 branches 70 tags 52 MiB
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516 commits

Author SHA1 Message Date
Emil J. Tywoniak
6f3b384ac4 rtlil: add source tracking to CaseRule actions 
(cherry picked from commit c36370f227)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
dad4961221 rtlil: replace SigSig actions with new type SyncAction 
(cherry picked from commit 94a53e08bc)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
9552cba923 rtlil: options for dumping twines 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
92b16718c9 twine: fix replayability, reduce TwineSearch usage 2026-07-20 13:57:10 +02:00
Emil J. Tywoniak
c08fb7f3ed WIP migration to twine 2026-07-20 12:27:18 +02:00
Emil J. Tywoniak
65f35a88eb WIP migration to twine 2026-07-20 12:27:18 +02:00
Emil J. Tywoniak
0f884b6cba twine: avoid TwinePool::lookup 2026-07-20 12:27:18 +02:00
Emil J. Tywoniak
a5248849d9 WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
b01a3694f0 WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
77ad54139e WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
e952044215 WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
7422b71802 WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
1210d8e117 WIP 2026-07-20 12:27:02 +02:00
Emil J. Tywoniak
6cd77a9af6 twine: start indexable colony with integer indices including preallocated twines 2026-07-20 12:27:02 +02:00
Emil J. Tywoniak
30bc1c23ee WIP 2026-07-20 12:27:02 +02:00
Emil J. Tywoniak
10436f31cd WIP 2026-07-20 12:27:02 +02:00
Emil J. Tywoniak
f508244f36 rtlil: fix masquerade 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
edb43b93d7 rtlil: introduce ModuleNameMasq (KNOWN BROKEN, do not merge) 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
be4d67d1a3 rtlil: replace AttrObject::meta_idx_ with ObjMeta pointer 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
84c6c61736 rtlil: extend per-Design meta vector to hold name slot 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
d7f88dd3a0 rtlil: evacuate src_id_ from AttrObject to per-Design meta vector 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
0bff07d55c rtlil: add Module* back-pointer to RTLIL::Memory 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
d37581d9d7 rtlil: add per-Design src meta vector + freelist 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
452964e75a rtlil: add Module* back-pointer to inner-process AttrObjects 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
f017bb8a93 twine 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
2c107f19e8 rtlil, patch: incremental signorm via connect_incremental, replacing batched sigNormalize in Patch::patch 2026-07-17 23:48:54 +02:00
Emil J. Tywoniak
c7a8fe1c79 rtlil, patch: update signorm index and driver fields when committing Cell from Patch to Design 2026-07-17 23:48:06 +02:00
Emil J. Tywoniak
07d5115135 patch: source transfer 2026-07-17 23:48:06 +02:00
Emil J. Tywoniak
277b6f47dc rtlil: add CellAdderMixin for shared Cell adder interface between Module and Patch 2026-07-17 23:48:00 +02:00
Emil J. Tywoniak
62cd00aeeb rtlil: allow friends to use Wire constructors with a factory token pattern 2026-07-17 23:47:08 +02:00
Emil J. Tywoniak
20b0a9934b rtlil: allow friends to use Cell constructors with a factory token pattern 2026-07-17 23:47:08 +02:00
Emil J. Tywoniak
77dd01edfc patcher: start 2026-07-17 23:47:08 +02:00
Emil J. Tywoniak
f2e5bcb86a rtlil: publish signorm fanout 2026-07-17 23:38:01 +02:00
Emil J. Tywoniak
3010c0fc31 signorm: add timers 2026-07-17 23:38:01 +02:00
Emil J. Tywoniak
b408a059ad rtlil: add dump_sigmap for hacky signorm debugging 2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
a7b62c6bc3 rtlil: forbid rewrite_sigspecs in signorm 2026-07-17 23:32:34 +02:00
Jannis Harder
b84beb598f WIP half broken snapshot 2026-07-17 23:32:20 +02:00
Michael Baier
58fc67ee66 Adding Width check to resize 2026-07-09 14:34:56 +02:00
Michael Baier
ea41b196da Adding Widht Limit 2026-07-09 14:34:56 +02:00
nella
7d3e56523b Preserve param signedness across overrides. 2026-05-13 16:25:15 +02:00
Emil J. Tywoniak
10bbda93f7 rtlil: extend SigSpec::extract test 2026-04-24 11:04:19 +02:00
Emil J. Tywoniak
25b9b796c4 rtlil: complicate extract again for packing 2026-04-24 11:04:19 +02:00
Robert O'Callahan
b42bb05b63 Parallelize Design::check() 2026-03-06 02:03:21 +00:00
Robert O'Callahan
7af5dbae35 Add IdString::unescape() method 
We've already talked about adding this as an alternative to `log_id()`, and we'll
need it later in this PR.
 2026-03-06 02:03:21 +00:00
nella
04822c6660 Readd builtin_ff_cell_types for plugin parity. 2026-03-04 12:39:45 +01:00
nella
66bd4716cf rtlil use newcelltypes. 2026-03-04 12:39:45 +01:00
Natalia
cf511628b0 modify generator for pyosys/wrappers.cc instead of headers 2026-01-18 02:11:09 -08:00
Natalia
fb864e91ee Add Design::run_pass() API for programmatic pass execution 
This commit adds a new run_pass() method to the RTLIL::Design class,
providing a convenient API for executing Yosys passes programmatically.

This is particularly useful for PyYosys users who want to run passes
on a design object without needing to manually construct Pass::call()
invocations. The method wraps Pass::call() with appropriate logging
to maintain consistency with command-line pass execution.

Example usage (from Python):
    design = ys.Design()
    # ... build or load design ...
    design.run_pass("hierarchy")
    design.run_pass("proc")
    design.run_pass("opt")

Changes:
- kernel/rtlil.h: Add run_pass() method declaration
- kernel/rtlil.cc: Implement run_pass() method
- tests/unit/kernel/test_design_run_pass.cc: Add unit tests
 2026-01-14 17:35:45 -08:00
nella
210b733555 Add rtlil string getters 2026-01-14 15:37:18 +01:00
Robert O'Callahan
8da919587d Parallelize opt_merge. 
I'm not sure why but this is actually faster than existing `opt_merge` even with
YOSYS_MAX_THREADS=1, for the jpeg synthesis test. 16.0s before, 15.5s after for
end-to-end synthesis.
 2026-01-08 04:21:39 +00:00