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Author	SHA1	Message	Date
Akash Levy	0b46d8b201	Merge pull request #109 from Silimate/clkgate_attr ... Added is_clock_gated attr to flops created via clockgate.cc pass	2026-02-20 17:02:02 -08:00
Akash Levy	c47dd20140	Merge pull request #108 from Silimate/icg_builtin_sim ... Added built in cell alongside sim support for cell	2026-02-20 17:01:20 -08:00
AdvaySingh1	ec537b189f	Added is_clock_gated attr to flops created via clockgate.cc pass	2026-02-20 11:34:50 -08:00
AdvaySingh1	8f5b8cb46c	Added is_clock_gated attr to flops created via clockgate.cc pass	2026-02-20 11:34:08 -08:00
Gus Smith	b454582f54	Detect undriven and error/warn	2026-02-20 11:00:59 -08:00
Gus Smith	cdc728b6f0	Suggest use of YW when possible	2026-02-20 09:33:51 -08:00
Miodrag Milanović	fb653c4181	Merge pull request #5700 from YosysHQ/wasi_speedup ... CI: WASI - Applying YoWASP changes to script	2026-02-20 18:00:24 +01:00
Miodrag Milanovic	68e47ebcfe	CI: WASI - Applying YoWASP changes to script	2026-02-20 15:23:45 +01:00
Miodrag Milanović	0ed7c5ad53	Merge pull request #5620 from YosysHQ/lofty/abc9-verify ... abc9: verify post-mapping equivalence by default	2026-02-20 13:41:11 +01:00
Krystine Sherwin	094481739f	memory_libmap: Add -force-params ... Reduce complexity for adi brams by unconditionally providing the WIDTH and ABITS parameters.	2026-02-20 10:57:00 +00:00
Emil J	13795203a1	Merge pull request #5680 from YosysHQ/emi/aiger-add-bounds-checks ... aigerparse: add some bounds checks	2026-02-20 11:53:49 +01:00
Emil J	74f7b0cf92	Merge pull request #5685 from chathhorn-galois/chathhorn/issue5684 ... Fix segfault from shift with 0-width signed arg.	2026-02-20 11:53:05 +01:00
Emil J	53509a9b2a	Merge pull request #5692 from YosysHQ/emil/modtools-fix-db-port-deletion ... modtools: fix database sanity	2026-02-20 10:49:28 +01:00
AdvaySingh1	84a03a6b9a	Merge branch 'icg_builtin_sim' into sat_clkgate	2026-02-19 11:51:49 -08:00
AdvaySingh1	b29514fafc	Added built in cell alongside sim support for cell	2026-02-19 11:48:35 -08:00
AdvaySingh1	d9867fc7c7	Merge branch 'main' into sat_clkgate	2026-02-19 09:43:22 -08:00
AdvaySingh1	5e58bf22e0	Changed param naming for consistancy	2026-02-19 09:42:59 -08:00
Akash Levy	723ddd74cf	Improve wreduce runtime	2026-02-19 01:03:26 -08:00
Miodrag Milanović	679156d323	Merge pull request #5686 from YosysHQ/version_bump ... Automatic version bump	2026-02-19 09:52:22 +01:00
Akash Levy	bf4ce9d6f7	Import uniquify fix	2026-02-19 00:24:32 -08:00
Akash Levy	3e9a5c68b1	Switch back to main Verific without VHDL support	2026-02-18 21:57:14 -08:00
Akash Levy	9a30512cff	Merge pull request #107 from Silimate/clkgate_node_retention ... Added node retention	2026-02-18 18:17:27 -08:00
AdvaySingh1	5769cdbea8	Added node retention	2026-02-18 16:05:56 -08:00
AdvaySingh1	d84e56ecac	Added naming for the new icg cells	2026-02-18 16:03:34 -08:00
Emil J. Tywoniak	abc7563a35	modtools: add ModIndex unit test	2026-02-18 22:15:44 +01:00
Emil J. Tywoniak	c75d80905a	modtools: fix database sanity on wire name swap	2026-02-18 21:23:21 +01:00
Akash Levy	b7098e8383	Merge branch 'YosysHQ:main' into main	2026-02-18 09:44:25 -08:00
AdvaySingh1	ee896b9eee	Removed sorting of similar candidate_gates for unnessessary optimization	2026-02-18 09:08:25 -08:00
Gus Smith	29a270c4b6	Merge pull request #5675 from rowanG077/add-missing-celledges ... kernel/celledges: cover more cell types	2026-02-18 07:50:41 -08:00
Miodrag Milanovic	5bb31485b7	Display repo and branch when applicable	2026-02-18 13:34:36 +01:00
Emil J. Tywoniak	62f19cb3a9	modtools: fix port_del db erase	2026-02-18 12:20:36 +01:00
Emil J	33a2de9635	Merge pull request #5681 from YosysHQ/emil/blifparse-bounds-check ... blifparse: add bounds check	2026-02-18 12:18:05 +01:00
Akash Levy	650c636d39	Fixups	2026-02-18 01:12:35 -08:00
nella	01e89a8f9e	Remove cell mentions.	2026-02-18 09:29:35 +01:00
nella	2b4f481850	Cleanup docs.	2026-02-18 09:24:41 +01:00
Akash Levy	33c2c88fa4	Bump Yosys to latest from upstream	2026-02-17 23:41:39 -08:00
Akash Levy	c04975b78c	Remove custom mux opt_exprs	2026-02-17 20:41:29 -08:00
AdvaySingh1	6cb9fadded	Removed downstream signals causing equiv_opt failures due to feedback loop	2026-02-17 16:22:59 -08:00
AdvaySingh1	90dbb91cae	Changed min cone size	2026-02-17 16:22:05 -08:00
AdvaySingh1	2ab89e1146	Passing equiv_opt pass and speed boosts	2026-02-17 16:13:51 -08:00
AdvaySingh1	c8b6869e65	Removed optimizations from infer_ce.cc for profiling	2026-02-17 15:20:57 -08:00
AdvaySingh1	a8e4fccc56	Removed simulation and isValidGatingSignal function	2026-02-17 14:07:22 -08:00
AdvaySingh1	fa9e7a77d7	Removed normal clockgate pass options form sate_clockgate pass	2026-02-17 13:43:22 -08:00
AdvaySingh1	efcabb270f	Added caching of simulation runs for speed	2026-02-17 13:38:32 -08:00
AdvaySingh1	dc4ca2c621	Added TODO for eliminating false paths	2026-02-17 12:42:20 -08:00
AdvaySingh1	499e83a549	Switched to using CE module. Mostly retaining SAT gates. Still needs speedup	2026-02-17 12:41:59 -08:00
AdvaySingh1	e755f6c42e	Added initial simulation. Incorrect simulation -- changed the number of accedpted results as well as increasing runtime	2026-02-17 12:14:53 -08:00
AdvaySingh1	2212d85626	Changed configurations to match the OpenROAD project	2026-02-17 11:57:56 -08:00
AdvaySingh1	144db54c4e	Changed to inverse hashing for more flexibility	2026-02-17 11:53:06 -08:00
AdvaySingh1	f0de3ae8de	Initial sat_clockgate pass pre speed optimization	2026-02-17 11:19:18 -08:00