Dan Ravensloft
c78ab8ebc5
synth_intel: rename for consistency with #1184
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Also fix a typo in the help message.
2019-07-18 16:46:21 +01:00
Eddie Hung
c76607b9bc
Wrong wildcard symbol
2019-07-18 08:14:58 -07:00
Eddie Hung
20b7120d66
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
2019-07-18 08:11:33 -07:00
Clifford Wolf
e66e8fb59d
Merge pull request #1184 from whitequark/synth-better-labels
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synth_{ice40,ecp5}: more sensible pass label naming
2019-07-18 15:34:28 +02:00
Clifford Wolf
927f0caa9d
Merge pull request #1203 from whitequark/write_verilog-zero-width-values
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write_verilog: dump zero width constants correctly
2019-07-18 15:31:27 +02:00
David Shah
16b0ccf04c
mul2dsp: Lower partial products always have unsigned inputs
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-18 11:33:37 +01:00
Eddie Hung
e3f8e59f18
Make all operands signed
2019-07-17 14:25:40 -07:00
Eddie Hung
58e63feae1
Update comment
2019-07-17 13:26:17 -07:00
Eddie Hung
91629ee4b3
Pattern matcher to check pool of bits, not exactly
2019-07-17 12:45:25 -07:00
Eddie Hung
8dca8d486e
Fix mul2dsp signedness
2019-07-17 12:44:52 -07:00
Eddie Hung
1b62b82e05
A_SIGNED == B_SIGNED so flip both
2019-07-17 11:34:18 -07:00
Eddie Hung
d63f105708
SigSpec::remove_const() to return SigSpec&
2019-07-17 10:44:11 -07:00
Clifford Wolf
56c00e871f
Remove old $pmux_safe code from write_verilog
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-17 11:49:04 +02:00
David Shah
82153059a1
Merge pull request #1204 from smunaut/fix_1187
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ice40: Adapt the relut process passes to the new $lut/SB_LUT4 port map
2019-07-17 07:55:26 +01:00
Eddie Hung
0b6d47f8bf
Add DSP_{A,B}_SIGNEDONLY macro
2019-07-16 15:55:13 -07:00
Eddie Hung
c501aa5ee8
Signedness
2019-07-16 15:54:27 -07:00
Eddie Hung
3f677fb0db
Signed extension
2019-07-16 15:54:07 -07:00
Sylvain Munaut
f28e38de99
ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map
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The new mapping introduced in 437fec0d88Fixes #1187
(Diagnosis of the issue by @daveshah1 on IRC)
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-07-16 23:57:15 +02:00
Eddie Hung
6390c535ba
Revert drop down to 24x16 multipliers for all
2019-07-16 14:30:25 -07:00
Eddie Hung
569cd66764
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
2019-07-16 14:18:36 -07:00
Eddie Hung
9616dbd125
Add support {A,B,P}REG packing
2019-07-16 14:06:32 -07:00
Eddie Hung
d086dfb5b0
SigSpec::extract to allow negative length
2019-07-16 14:06:07 -07:00
Eddie Hung
5d1ce04381
Add support for {A,B,P}REG in DSP48E1
2019-07-16 14:05:50 -07:00
whitequark
4ff44d85a5
write_verilog: dump zero width constants correctly.
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Before this commit, zero width constants were dumped as "" (empty
string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty
string is equivalent to "\0", and is 8 bits wide, so that's wrong.
After this commit, a replication operation with a count of zero is
used instead, which is explicitly permitted per 1364-2005 5.1.14,
and is defined to have size zero. (Its operand has to have a non-zero
size for it to be legal, though.)
Fixes #948 (again).
2019-07-16 21:00:09 +00:00
Eddie Hung
f8e470c1d1
Merge pull request #1202 from YosysHQ/cmp2lut_lut6
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cmp2lut transformation to support >32 bit LUT masks
2019-07-16 13:52:43 -07:00
whitequark
698ab9beee
synth_ecp5: rename dram to lutram everywhere.
2019-07-16 20:45:12 +00:00
whitequark
ba099bfe9b
synth_{ice40,ecp5}: more sensible pass label naming.
2019-07-16 20:41:51 +00:00
Eddie Hung
7a58ee78dc
gen_lut to return correctly sized LUT mask
2019-07-16 12:45:29 -07:00
Eddie Hung
8a2a2cd035
Forgot to commit
2019-07-16 12:44:26 -07:00
Eddie Hung
dd10d2b00d
Add tests for cmp2lut on LUT6
2019-07-16 12:11:59 -07:00
David Shah
d38df68d26
xilinx: Add correct signed behaviour to DSP48E1 model
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-16 17:53:08 +01:00
Eddie Hung
5939b5d636
Merge pull request #1188 from YosysHQ/eddie/abc9_push_inverters
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abc9: push inverters driving box inputs (comb outputs) through $lut soft logic
2019-07-16 08:53:47 -07:00
Eddie Hung
ba8ccbdea8
Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
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abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
2019-07-16 08:52:14 -07:00
David Shah
95c8d27b0b
xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed)
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-16 16:47:53 +01:00
David Shah
8da4c1ad82
mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTH
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-16 16:44:40 +01:00
David Shah
7a75f5f3ac
mul2dsp: Fix indentation
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-16 16:19:32 +01:00
Clifford Wolf
a1a04ea79c
Merge pull request #1200 from mmicko/fix_typo_liberty_cc
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Fix typo, double "of"
2019-07-16 15:27:25 +02:00
Clifford Wolf
928f0a4438
Merge pull request #1199 from mmicko/extract_fa_fix
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Fix check logic in extract_fa
2019-07-16 15:27:09 +02:00
Miodrag Milanovic
6cce679b35
Fix typo, double "of"
2019-07-16 11:03:30 +02:00
Miodrag Milanovic
2b469e82a7
Fix check logic in extract_fa
2019-07-16 10:35:18 +02:00
Eddie Hung
fd5b3593d8
Do not swap if equals
2019-07-15 16:52:37 -07:00
Eddie Hung
b29f26f6c7
SigSpec::extend_u0() to return *this
2019-07-15 16:23:12 -07:00
Eddie Hung
5f00d335d4
Oops forgot these files
2019-07-15 15:03:15 -07:00
Eddie Hung
dd59375a66
Add xilinx_dsp for register packing
2019-07-15 14:46:31 -07:00
Eddie Hung
42f8e68e76
OUT port to Y in generic DSP
2019-07-15 14:45:47 -07:00
Eddie Hung
0c7ee6d0fa
Move DSP mapping back out to dsp_map.v
2019-07-15 14:18:44 -07:00
Eddie Hung
87db41a2bb
Merge pull request #1196 from YosysHQ/eddie/fix1178
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Fix different synth results between with and without debug output "-g"
2019-07-15 13:31:08 -07:00
Eddie Hung
5fb27c071b
$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark
2019-07-15 12:03:51 -07:00
Eddie Hung
91fcf034bc
Only swap if B_WIDTH > A_WIDTH
2019-07-15 11:24:11 -07:00
Eddie Hung
1793e6018a
Tidy up
2019-07-15 11:19:54 -07:00
