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Code Activity
5176 commits 99 branches 53 tags 46 MiB
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896 commits

Author SHA1 Message Date
Clifford Wolf
7cfae2c52f Use mem2reg on memories that only have constant-index write ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-01 13:35:09 -08:00
Clifford Wolf
60e3c38054 Improve "read" error msg 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-28 20:34:42 -08:00
Clifford Wolf
1816fe06af Fix handling of defparam for when default_nettype is none 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-24 20:09:41 +01:00
Clifford Wolf
a516b4fb5a Check if Verific was built with DB_PRESERVE_INITIAL_VALUE 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-24 19:51:30 +01:00
Clifford Wolf
23148ffae1 Fixes related to handling of autowires and upto-ranges, fixes #814 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 18:40:11 +01:00
Clifford Wolf
974927adcf Fix handling of expression width in $past, fixes #810 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 17:55:33 +01:00
Clifford Wolf
28fba903c5 Fix segfault in printing of some internal error messages 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 17:40:52 +01:00
Eddie Hung
843e7fc8a7 Fix for using POSIX basename 2019-02-19 09:02:37 -08:00
Eddie Hung
8e1dbfac3a Missing OSX headers? 2019-02-17 20:59:53 -08:00
Eddie Hung
9268a271fb read_aiger to ignore line after ands for ascii, not binary 2019-02-17 12:07:14 -08:00
Eddie Hung
03a533d102 Merge https://github.com/YosysHQ/yosys into read_aiger 2019-02-17 11:44:01 -08:00
Clifford Wolf
807b3c7697 Fix sign handling of real constants 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-13 12:36:47 +01:00
Eddie Hung
6faad18874 Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aiger 2019-02-12 09:21:46 -08:00
Eddie Hung
a2ae393811 Use module->add{Not,And}Gate() functions 2019-02-12 09:21:15 -08:00
Eddie Hung
04c580fde7 Do not break for constraints 2019-02-11 13:28:00 -08:00
Eddie Hung
727ba52504 No increment line_count for binary ANDs 2019-02-11 13:24:21 -08:00
Eddie Hung
bb4164481d Do not ignore newline after AND in binary AIG 2019-02-11 11:51:44 -08:00
Eddie Hung
8886fa5506 addDff -> addDffGate as per @daveshah1 2019-02-08 13:17:53 -08:00
Eddie Hung
afc3c4b613 Fix tabulation 2019-02-08 13:17:02 -08:00
Eddie Hung
aa66d8f12f -module_name arg to go before -clk_name 2019-02-08 12:49:55 -08:00
Eddie Hung
391ec75b07 Add missing "[options]" to read_blif help 2019-02-08 12:41:39 -08:00
Eddie Hung
fb8ad440a3 Allow module name to be determined by argument too 2019-02-08 12:40:43 -08:00
Eddie Hung
f1befe1b44 Refactor into AigerReader class 2019-02-08 12:04:26 -08:00
Eddie Hung
2a8cc36578 Parse binary AIG files 2019-02-08 11:45:16 -08:00
Eddie Hung
09d758f0a3 Refactor to parse_aiger_header() 2019-02-08 10:54:31 -08:00
Eddie Hung
36c56bf412 Add comment 2019-02-08 08:37:44 -08:00
Eddie Hung
5e24251a61 Handle reset logic in latches 2019-02-08 08:37:18 -08:00
Eddie Hung
652e414392 Change literal vars from int to unsigned 2019-02-08 08:09:30 -08:00
Eddie Hung
fafa972238 Create clk outside of latch loop 2019-02-08 08:08:49 -08:00
Eddie Hung
02f603ac1a Handle latch symbols too 2019-02-08 08:05:27 -08:00
Eddie Hung
5a593ff41c Remove return after log_error 2019-02-08 08:04:48 -08:00
Eddie Hung
6dbeda1807 Add support for symbol tables 2019-02-08 08:03:40 -08:00
Eddie Hung
791f93181d Stub for binary AIGER 2019-02-08 07:31:04 -08:00
Eddie Hung
40db2f2eb6 Refactor 2019-02-06 14:58:47 -08:00
Eddie Hung
cc0b723484 WIP 2019-02-06 12:19:48 -08:00
Clifford Wolf
17ceab92a9 Bugfix in Verilog string handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-05 12:10:24 +01:00
Clifford Wolf
6d1e7e9403 Remove -m32 Verific eval lib build instructions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-04 15:03:49 +01:00
Clifford Wolf
1eb101a38a Improve VerificImporter support for writes to asymmetric memories 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-02 15:33:43 +01:00
Clifford Wolf
50b09de033 Fix VerificImporter asymmetric memories error message 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-02 15:05:23 +01:00
whitequark
efa278e232 Fix typographical and grammatical errors and inconsistencies. 
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
 2019-01-02 13:12:17 +00:00
Clifford Wolf
6dad191377 Add "read_ilang -[no]overwrite" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-23 15:45:09 +01:00
Clifford Wolf
fdf7c42181 Fix segfault in AST simplify 
(as proposed by Dan Gisselquist)

Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-18 17:49:38 +01:00
Clifford Wolf
3d671630e2 Improve src tagging (using names and attrs) of cells and wires in verific front-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-18 16:01:22 +01:00
whitequark
4effb38e6d read_ilang: allow slicing sigspecs. 2018-12-16 17:53:26 +00:00
Sylvain Munaut
58fb2ac818 verilog_parser: Properly handle recursion when processing attributes 
Fixes #737

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-12-14 12:48:00 +01:00
Clifford Wolf
910d94b212 Verific updates 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-06 07:21:50 +01:00
Sylvain Munaut
86ce43999e Make return value of $clog2 signed 
As per Verilog 2005 - 17.11.1.

Fixes #708

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-24 18:49:23 +01:00
Clifford Wolf
5387ccb041 Set Verific flag vhdl_support_variable_slice=1 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-09 21:03:23 +01:00
Clifford Wolf
719e29404a Allow square brackets in liberty identifiers 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-05 12:33:33 +01:00
Clifford Wolf
36ea98385f Add warning for SV "restrict" without "property" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-04 15:57:17 +01:00