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Author SHA1 Message Date
Natalia
6bf9fc1817 Add -nocells flag to equiv_make and equiv_opt 
The -nocells flag skips cell equivalence checking and only checks wire
equivalence. This is useful when optimizations preserve functionality but
rename or restructure cells, avoiding false negatives in equivalence checking.
 2026-01-15 16:01:07 -08:00
github-actions[bot]
967b47d984 Bump version 2026-01-15 00:24:54 +00:00
nella
763001885f
Merge pull request #5608 from YosysHQ/nella/rtlil-to-string 
Add rtlil string getters
 2026-01-14 19:00:47 +01:00
nella
210b733555 Add rtlil string getters 2026-01-14 15:37:18 +01:00
github-actions[bot]
4c1a18f01d Bump version 2026-01-14 06:40:44 +00:00
Emil J
71feb2a2a1
Merge pull request #5604 from YosysHQ/emil/read_verilog-remove-log 
read_verilog: remove log I left behind by accident
 2026-01-13 17:48:30 +00:00
Emil J. Tywoniak
83c1364eeb read_verilog: remove log I left behind by accident 2026-01-13 18:47:23 +01:00
Emil J
8da113b7f0
Merge pull request #5502 from YosysHQ/emil/digit-separator 
Use digit separators for large decimal integers
 2026-01-13 17:42:24 +00:00
Emil J
d9956b20f8
Merge pull request #5603 from YosysHQ/emil/makefile-no-ast-header 
Makefile: no longer install ast.h and ast_binding.h
 2026-01-13 17:18:40 +00:00
Emil J
ff3c24fcdc
Merge pull request #5521 from YosysHQ/emil/merge-queues 
.github: trigger everything that triggers on main or PRs on merge queue
 2026-01-13 17:22:37 +01:00
Emil J
5ba0e9cae3
Merge pull request #4235 from ylm/genblk_wire 
Add autowires in genblk/for expension
 2026-01-13 16:40:22 +01:00
Emil J. Tywoniak
8e2038c419 Use digit separators for large decimal integers 2026-01-13 16:38:12 +01:00
Emil J. Tywoniak
21e6833010 Makefile: no longer install ast.h and ast_binding.h 2026-01-13 16:33:11 +01:00
Miodrag Milanović
8f00c1824f
Merge pull request #5602 from YosysHQ/year_update 
Update year in banner and license
 2026-01-13 15:30:42 +01:00
Miodrag Milanovic
0e6973037d Update year in banner and license 2026-01-13 14:23:51 +01:00
nella
b332279baf
Merge pull request #5592 from YosysHQ/gus/5503-yw-load-error-msg 
More helpful error messages when loading Yosys Witness files with `yosys-smtbmc`
 2026-01-13 12:00:06 +01:00
Miodrag Milanović
77005b69a2
Merge pull request #5601 from YosysHQ/release/v0.61 
Release version 0.61
 2026-01-13 09:39:50 +01:00
Miodrag Milanovic
b08e044994 Next dev cycle 2026-01-13 09:24:49 +01:00
Miodrag Milanovic
5ae48ee25f Release version 0.61 2026-01-13 08:35:02 +01:00
Miodrag Milanović
51b210c93c
Merge pull request #5600 from YosysHQ/fix_musllinux 
musllinux fix so wheels build can work
 2026-01-13 07:08:04 +01:00
github-actions[bot]
78cbc21b94 Bump version 2026-01-13 00:22:49 +00:00
Emil J
cc25ccfcd7
Merge pull request #5559 from nataliakokoromyti/upstream-lut2bmux 
add lut2bmux
 2026-01-12 16:09:13 +01:00
Miodrag Milanovic
b3b71df07c musllinux fix so wheels build can work 2026-01-12 15:38:45 +01:00
Miodrag Milanović
72690062a1
Merge pull request #5599 from YosysHQ/musllinux_fix 
musllinux fix so wheels build can work
 2026-01-12 14:00:00 +01:00
Emil J
f193dd0a28
Merge pull request #5594 from rocallahan/sdc-workaround 
Check for missing port in SDC code to work around compiler bug
 2026-01-12 11:22:25 +01:00
Miodrag Milanovic
2b12b74121 musllinux fix so wheels build can work 2026-01-11 15:23:38 +01:00
Robert O'Callahan
37347aacb2 Check for missing port in SDC code 
I am getting weird crashes on `main` in `tests/sdc/alu_sub.ys` which I traced to a null `Wire*`
in `SdcObjects::constrained_ports`. The null `Wire*` is being set in the `SdcObjects`
constructor. I don't understand what's going on here, so I added this check to detect the
missing wire early ... and that made the crash go away. Compiler bug maybe? I have
`Debian clang version 19.1.7 (3+build5)`, default build configuration.

Anyway this code seems fine to have.
 2026-01-10 04:00:17 +00:00
github-actions[bot]
991e704899 Bump version 2026-01-09 00:26:46 +00:00
KrystalDelusion
cc3d569ade
Merge pull request #5591 from YosysHQ/krys/clean_empty_switch 
Improve handling of empty switches
 2026-01-09 11:52:27 +13:00
Emil J
c7b839ef5a
Merge pull request #5530 from rocallahan/parallel-opt-merge 
Parallelize `opt_merge`
 2026-01-08 10:43:44 +01:00
Robert O'Callahan
8da919587d Parallelize opt_merge. 
I'm not sure why but this is actually faster than existing `opt_merge` even with
YOSYS_MAX_THREADS=1, for the jpeg synthesis test. 16.0s before, 15.5s after for
end-to-end synthesis.
 2026-01-08 04:21:39 +00:00
github-actions[bot]
35321cd292 Bump version 2026-01-07 00:25:36 +00:00
Krystine Sherwin
9a09758f56
Test empty switches 2026-01-07 13:21:33 +13:00
Gus Smith
4d237bdd92 Deliver more helpful error messages 2026-01-06 16:19:54 -08:00
Gus Smith
9f77465170 Add test 2026-01-06 16:19:04 -08:00
Krystine Sherwin
c0e29ef57c
proc_clean: Removing an empty full_case is doing something 2026-01-07 13:10:32 +13:00
Krystine Sherwin
fcb8695261
write_verilog: Skip empty switches 2026-01-07 13:09:49 +13:00
Emil J
0ab967b036
Merge pull request #5564 from rocallahan/pass-fuzz 
Add support for fuzz-test comparison of two passes intended to give identical RTLIL results
 2026-01-06 20:07:31 +01:00
Emil J
5c630a366d
Merge pull request #5555 from rocallahan/defer-redirects 
Defer redirecting cell outputs when merging cells in `opt_merge` untill after we've done a full pass over the cells.
 2026-01-06 18:48:16 +01:00
Robert O'Callahan
042ec1cf60 Defer redirecting cell outputs when merging cells in opt_merge until after we've done a full pass over the cells. 
This avoids changing `assign_map` and `initvals`, which are inputs to the hash function for `known_cells`,
while `known_cells` exists. Changing the hash function for a hashtable while it exists leads to
confusing behavior. That also means the exact behavior of `opt_merge` cannot be reproduced by a
parallel implementation.
 2026-01-06 16:21:48 +00:00
Emil J
2e1a2cfacb
Merge pull request #5561 from YosysHQ/emil/opt_expr-test-avoid-multiple-drivers 
opt_expr: avoid multiple drivers in test
 2026-01-06 14:54:55 +01:00
Natalia
11b0e7ad92 add lut2bmux 2026-01-06 14:48:16 +01:00
github-actions[bot]
1567526954 Bump version 2026-01-06 00:26:49 +00:00
Miodrag Milanović
1ccbd21ed8
Merge pull request #5587 from YosysHQ/update_abc 
Update ABC as per 2026-01-05
 2026-01-05 18:00:36 +01:00
Miodrag Milanovic
6e5a516051 Update ABC as per 2026-01-05 2026-01-05 16:34:45 +01:00
Miodrag Milanović
eae00c19a8
Merge pull request #5579 from yrabbit/gw5-bsram-be-w 
Gowin. Implement byte enable.
 2026-01-05 11:10:03 +01:00
YRabbit
8a78f2f7c5 Gowin. Fix style. 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2026-01-05 20:07:31 +10:00
Miodrag Milanović
ab4381fba4
Merge pull request #5576 from rocallahan/idstring-pod 
Give `IdString` a default move constructor and make it a POD type.
 2026-01-05 11:05:56 +01:00
YRabbit
ea90f54783 Gowin. Implement byte enable. 
Enable write port with byte enables for BSRAM primitives.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2026-01-03 17:42:49 +10:00
github-actions[bot]
8101c87fab Bump version 2025-12-31 00:27:01 +00:00