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Merge pull request #5555 from rocallahan/defer-redirects

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Defer redirecting cell outputs when merging cells in `opt_merge` untill after we've done a full pass over the cells.
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Emil J 2026-01-06 18:48:16 +01:00 • committed by GitHub
commit 5c630a366d
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1 changed files with 10 additions and 6 deletions
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16
passes/opt/opt_merge.cc
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@ -289,6 +289,7 @@ struct OptMergeWorker
CellPtrHash,
CellPtrEqual> known_cells (0, CellPtrHash(*this), CellPtrEqual(*this));
std::vector<RTLIL::SigSig> redirects;
for (auto cell : cells)
{
auto [cell_in_map, inserted] = known_cells.insert(cell);
@ -310,12 +311,7 @@ struct OptMergeWorker
RTLIL::SigSpec other_sig = other_cell->getPort(it.first);
log_debug(" Redirecting output %s: %s = %s\n", it.first,
log_signal(it.second), log_signal(other_sig));
Const init = initvals(other_sig);
initvals.remove_init(it.second);
initvals.remove_init(other_sig);
module->connect(RTLIL::SigSig(it.second, other_sig));
assign_map.add(it.second, other_sig);
initvals.set_init(other_sig, init);
redirects.push_back(RTLIL::SigSig(it.second, std::move(other_sig)));
}
}
log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type, cell->name, module->name);
@ -323,6 +319,14 @@ struct OptMergeWorker
total_count++;
}
}
for (const RTLIL::SigSig &redirect : redirects) {
module->connect(redirect);
Const init = initvals(redirect.second);
initvals.remove_init(redirect.first);
initvals.remove_init(redirect.second);
assign_map.add(redirect.first, redirect.second);
initvals.set_init(redirect.second, init);
}
}
log_suppressed();