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Author	SHA1	Message	Date
Emil J. Tywoniak	88aa5f190b	memory_bram: add -register	2026-05-22 18:39:05 +02:00
Emil J. Tywoniak	5e313a19a0	ffmerge: initvals signorm compatibility fixup	2026-05-22 18:39:05 +02:00
Emil J. Tywoniak	eb6dd47bd6	timinginfo: special-case $specify2 in signorm invariant	2026-05-22 18:39:04 +02:00
Emil J. Tywoniak	5bfb631085	opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped	2026-05-22 18:38:37 +02:00
Emil J. Tywoniak	bd8738de15	connect: remove input ports on conflict	2026-05-22 18:38:37 +02:00
Emil J. Tywoniak	aecc173f83	opt_dff: sigma harder, FfDataSigMapped	2026-05-22 18:38:37 +02:00
Emil J. Tywoniak	7382be6962	ff: add FfDataSigMapped	2026-05-22 18:38:37 +02:00
Emil J. Tywoniak	be7beaf91a	opt_dff: temporarily disable signorm due to muxtree traversal	2026-05-22 18:38:37 +02:00
Emil J. Tywoniak	95eae1aa6d	tests: fix rtlil roundtrip test	2026-05-22 18:38:36 +02:00
Emil J. Tywoniak	21bed1a411	design: fix signorm commit connectivity to design	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	6c2a90affc	cxxrtl: ignore $input_port	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	faa1a1065c	flatten: redo signormalization to work around fanout issue	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	bd437f207f	abstract: fix test signorm	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	4f665d6efc	signorm: disable passes that use rewrite_sigspecs	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	6447a39c0c	aiger: ignore $input_port	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	8267dee75a	check: stitch info about $connect ports together for driver analysis	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	b42136aa8c	signorm: remove $input cells when leaving	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	5c5df513d1	abstract: skip $input_port cells	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	dad6277a25	flatten: skip $input_port cells in template module	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	d541def612	signorm: skip const when fixing fanout	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	68bb5c6b94	signorm: disable in passes that use swap_names	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	4d2a6f2b7a	opt_expr: fix invert_map	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	422a505435	satgen: support $connect	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	fb03a34277	rtlil: add dump_sigmap for hacky signorm debugging	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	b859080ef2	techmap: disable signorm more	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	6575e7f1df	techmap: disable signorm	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	2f7d0913fc	opt_hier: disable signorm	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	6b06869242	timinginfo: disable output wire check due to signorm	2026-05-22 18:37:56 +02:00
Emil J. Tywoniak	6d08c53429	rtlil: forbid rewrite_sigspecs in signorm	2026-05-22 18:37:13 +02:00
Emil J. Tywoniak	bb2d6f0e2a	opt_merge_inc: re add initvals deletion	2026-05-22 18:37:13 +02:00
Emil J. Tywoniak	07628a4042	synth_ice40: always read abc9 model to understand port direction	2026-05-22 18:37:13 +02:00
Emil J. Tywoniak	5b6b11dd44	tests: adjust to input_port and init behavior (sketchy)	2026-05-22 18:37:13 +02:00
Emil J. Tywoniak	80a440ed2d	tests: adjust to input_port and init behavior (sketchy)	2026-05-22 18:37:13 +02:00
Emil J. Tywoniak	69c9f3e619	tests: adjust to input_port and init behavior (sketchy)	2026-05-22 18:37:13 +02:00
Emil J. Tywoniak	9d86a6636c	wreduce: fixup initvals after setPort	2026-05-22 18:37:13 +02:00
Emil J. Tywoniak	e5266d0fbc	ff: fixup initvals with signorm direct drive wire if it's created, not old driven wire	2026-05-22 18:37:13 +02:00
Emil J. Tywoniak	3dc45005f2	tests: adjust to input_port and init behavior (sketchy)	2026-05-22 18:37:13 +02:00
Emil J. Tywoniak	af48c1cdfb	rtlil: fix zero width SigSpec crash in signorm setPort unsetPort	2026-05-22 18:37:13 +02:00
Emil J. Tywoniak	80ca3174ea	bug2920: disable	2026-05-22 18:37:13 +02:00
Emil J. Tywoniak	e6515cfd93	rtlil_bufnorm: fix cell deletion deferral bug	2026-05-22 18:37:13 +02:00
Emil J. Tywoniak	28013eccbc	tests: adjust to input_port and init behavior (sketchy)	2026-05-22 18:37:13 +02:00
Emil J. Tywoniak	dcc4cbea2f	check: don't fail on $input_port	2026-05-22 18:37:13 +02:00
Emil J. Tywoniak	8c4816c802	mem: fix signorm cell type morph	2026-05-22 18:37:13 +02:00
Jannis Harder	423c8be71b	WIP half broken snapshot	2026-05-22 18:37:11 +02:00
Jannis Harder	30505c2cd6	WIP remove dead code	2026-05-22 18:34:52 +02:00
Miodrag Milanović	9d0cdb8551	Merge pull request #5901 from YosysHQ/test_cleanup ... Test out-of-tree build support	2026-05-20 10:55:28 +00:00
Miodrag Milanovic	4c8e61a52b	Expose SBY binary location	2026-05-19 16:08:21 +02:00
Miodrag Milanovic	07924a3c62	Use common.mk for sva tests as well	2026-05-19 15:15:41 +02:00
Miodrag Milanovic	2b3f4c37f5	Fix functional tests	2026-05-19 14:42:08 +02:00
Miodrag Milanovic	15e09163cd	Do not use Makefile.conf	2026-05-19 14:29:06 +02:00