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Code Activity
15917 commits 122 branches 59 tags 72 MiB
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4629 commits

Author SHA1 Message Date
Miodrag Milanovic
ad48639cdd Start restoring memory state from VCD/FST 2022-05-04 10:41:04 +02:00
Miodrag Milanovic
3730db4b98 AIM file could have gaps in or between inputs and inits 2022-05-02 11:18:30 +02:00
Jannis Harder
e0e31bfc5c
Merge pull request #3257 from jix/tribuf-formal 
tribuf: `-formal` option: convert all to logic and detect conflicts
 2022-04-25 16:23:06 +02:00
Miodrag Milanovic
bbfdea2f8a Match $anyseq input if connected to public wire 2022-04-22 17:20:17 +02:00
Miodrag Milanovic
4d80bc24c7 Treat $anyseq as input from FST 2022-04-22 16:23:39 +02:00
Miodrag Milanovic
33f4009bb5 Last sample from input does not represent change 2022-04-22 13:46:11 +02:00
Miodrag Milanovic
83cad82b29 latches are always set to zero 2022-04-22 12:04:05 +02:00
Miodrag Milanovic
c989adcc2d If not multiclock, output only on clock edges 2022-04-22 12:03:39 +02:00
Miodrag Milanovic
75032a565d Set init state for all wires from FST and set past 2022-04-22 11:57:39 +02:00
Miodrag Milanovic
8fa2f3b260 Fix multiclock for btor2 witness 2022-04-22 11:53:41 +02:00
Miodrag Milanović
c3a3f68b4d
Merge pull request #3280 from YosysHQ/micko/fix_readaiw 
Fix reading aiw from other solvers
 2022-04-18 09:49:21 +02:00
Marcelina Kościelnicka
25ff83f0b5 memory_share: Fix up mismatched address widths. 2022-04-15 22:01:00 +02:00
Marcelina Kościelnicka
48eea3efcf opt_dff: Fix behavior on $ff with D == Q. 2022-04-15 22:00:32 +02:00
Miodrag Milanovic
9508bb2330 Fix reading aiw from other solvers 2022-04-15 11:45:16 +02:00
Jannis Harder
bc48500548 tribuf: -formal option: convert all to logic and detect conflicts 2022-04-12 12:46:22 +02:00
Miodrag Milanovic
868409361c Use wrap_async_control_gate if ff is fine 2022-04-08 16:30:29 +02:00
Iris Johnson
ccc6060f52 Makefile: properly conditionalize features requiring compression. 2022-04-07 20:07:44 -05:00
Catherine
8a1d531b25
Merge pull request #3269 from YosysHQ/micko/fix_autotop 
Reorder steps in -auto-top to fix synth command, fixes #3261
 2022-04-07 22:40:35 +00:00
Marcelina Kościelnicka
376d8cb26f abc: Add support for FFs with reset in -dff 2022-04-07 15:05:02 +02:00
Miodrag Milanovic
977002b1d2 Reorder steps in -auto-top to fix synth command, fixes #3261 2022-04-05 14:02:37 +02:00
Marcelina Kościelnicka
0aec79a0da show: Fix width labels. 
See #3266.
 2022-04-04 22:48:09 +02:00
Miodrag Milanovic
6020ba67ac past_ad initial value setting 2022-04-02 19:13:15 +02:00
Miodrag Milanovic
2c96ecc5f7 setInitState can be only one altering values 2022-04-02 19:13:15 +02:00
Miodrag Milanovic
b54aecd80a Set past_d value for init state 2022-04-02 19:13:15 +02:00
Jannis Harder
8ca9737180
Merge pull request #3264 from jix/invalid_ff_dcinit_merge 
opt_merge: Add `-keepdc` option required for formal verification
 2022-04-02 12:41:28 +02:00
Jannis Harder
ca5b910296 opt_merge: Add -keepdc option required for formal verification 
The `-keepdc` option prevents merging flipflops with dont-care bits in
their initial value, as, in general, this is not a valid transform for
formal verification.

The keepdc option of `opt` is passed along to `opt_merge` now.
 2022-04-01 21:03:20 +02:00
Miodrag Milanovic
86ce441af6 Set init values for wrapped async control signals 2022-04-01 17:44:00 +02:00
Miodrag Milanovic
c95b9b4ba5 Support memories in aiw and multiclock 2022-03-31 13:10:13 +02:00
Lofty
c1057cb3e0
Merge pull request #3194 from Ravenslofty/abc9-flow3mfs 
abc9: add flow3mfs script
 2022-03-28 15:51:04 +01:00
gatecat
8b64dc1dce abc9_ops: Also derive blackboxes with timing info 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-24 14:36:07 +00:00
Miodrag Milanovic
322ab1cd54 Proper SigBit forming in sim 2022-03-22 14:43:18 +01:00
Miodrag Milanovic
ff3b0c2c46 Proper SigBit forming in sim 2022-03-22 14:22:32 +01:00
Miodrag Milanovic
55eed8df57 More verbose warnings 2022-03-18 14:47:35 +01:00
Miodrag Milanovic
1f3423cd7d Recognize registers and set initial state for them in tb 2022-03-16 14:35:39 +01:00
Miodrag Milanovic
e217e3017a Update sim help message. 2022-03-16 07:55:57 +01:00
Miodrag Milanović
25d6fdfea7
Merge pull request #3232 from YosysHQ/micko/fst2tb 
Added fst2tb pass for generating testbench
 2022-03-14 20:01:55 +01:00
Miodrag Milanovic
f5c20b8286 Added fst2tb pass for generating testbench 2022-03-14 19:06:29 +01:00
Claire Xen
5e2992dae2
Merge pull request #3213 from antonblanchard/abc-typo 
abc: Fix {I} and {P} substitution
 2022-03-14 16:05:23 +01:00
Miodrag Milanović
cbece4af0c
Merge pull request #3229 from YosysHQ/micko/sim_date 
Add date parameter to enable full date/time and version info
 2022-03-11 19:02:57 +01:00
Claire Xenia Wolf
e21badd4b3 Add "sim -q" option 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-03-11 16:26:11 +01:00
Miodrag Milanovic
37de369ba7 Add date parameter to enable full date/time and version info 2022-03-11 16:01:59 +01:00
Claire Xenia Wolf
be32de1caa Small fix in "sim" help message 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-03-11 15:36:23 +01:00
Miodrag Milanovic
5204694123 FstData already do conversion to VCD 2022-03-11 15:21:36 +01:00
Miodrag Milanovic
b72c779204 Support cell name in btor witness file 2022-03-11 15:11:14 +01:00
Miodrag Milanovic
357336339a Proper write of memory data 2022-03-11 11:19:53 +01:00
Miodrag Milanovic
295b0d1899 Start work on memory init 2022-03-09 18:34:02 +01:00
Miodrag Milanovic
f37ac5d934 Fixes and error check 2022-03-09 09:48:29 +01:00
Miodrag Milanovic
ede348cdc2 cleanup 2022-03-07 16:32:32 +01:00
Miodrag Milanovic
1b1ecd4ab0 Error checks for aiger witness 2022-03-07 15:00:14 +01:00
Miodrag Milanovic
b6aca1d743 btor2 witness co-simulation 2022-03-07 13:59:36 +01:00