mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 03:32:29 +00:00
Code Activity

Fixes and error check

Browse source
This commit is contained in:
Miodrag Milanovic 2022-03-09 09:48:29 +01:00
parent ede348cdc2
commit f37ac5d934
1 changed files with 5 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

6
passes/sat/sim.cc
View file

@ -1095,6 +1095,8 @@ struct SimWorker : SimShared
void run_cosim_aiger_witness(Module *topmod)
{
log_assert(top == nullptr);
if ((clock.size()+clockn.size())==0)
log_error("Clock signal must be specified.\n");
std::ifstream mf(map_filename);
std::string type, symbol;
int variable, index;
@ -1213,6 +1215,8 @@ struct SimWorker : SimShared
void run_cosim_btor2_witness(Module *topmod)
{
log_assert(top == nullptr);
if ((clock.size()+clockn.size())==0)
log_error("Clock signal must be specified.\n");
std::ifstream f;
f.open(sim_filename.c_str());
if (f.fail() || GetSize(sim_filename) == 0)
@ -1278,7 +1282,7 @@ struct SimWorker : SimShared
if ((int)parts[1].size() != w->width)
log_error("Size of wire %s is different than provided data.\n", log_signal(w));
top->set_state(w, Const(parts[1]));
top->set_state(w, Const::from_string(parts[1]));
break;
}
}