mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 17:15:33 +00:00
Code Activity
11275 commits 94 branches 53 tags 45 MiB
Commit graph

11275 commits

This branch
This branch
All branches
Author SHA1 Message Date
Kamil Rakoczy
68c67c40ec
Fix access to whole sub-structs (#3086) 
* Add support for accessing whole struct
* Update tests

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2022-02-14 14:34:20 +01:00
github-actions[bot]
59738c09be Bump version 2022-02-13 01:02:04 +00:00
Marcelina Kościelnicka
3a62fa0c97 gowin: Add remaining block RAM blackboxes. 2022-02-12 11:48:57 +01:00
github-actions[bot]
1772a1e98e Bump version 2022-02-12 01:01:05 +00:00
Zachary Snow
15eb66b99d verilog: fix dynamic dynamic range asgn elab 2022-02-11 22:54:55 +01:00
Zachary Snow
90bb47d181 verilog: fix const func eval with upto variables 2022-02-11 21:01:51 +01:00
Claire Xen
ca876e7c12
Merge pull request #2376 from nmoroze/clk2ff-better-names 
clk2fflogic: nice names for autogenerated signals
 2022-02-11 17:30:32 +01:00
Miodrag Milanović
fc7d78f071
Merge pull request #3164 from zachjs/fix-ast-warn 
fix dumpAst() compilation warning
 2022-02-11 16:43:35 +01:00
Claire Xen
49545c73f7
Merge branch 'master' into clk2ff-better-names 2022-02-11 16:03:12 +01:00
Claire Xen
e016518866
Merge pull request #2019 from boqwxp/glift 
Add `glift` command for creating gate-level information flow tracking models and optimization problems
 2022-02-11 15:51:24 +01:00
github-actions[bot]
c8903e7053 Bump version 2022-02-10 00:58:51 +00:00
Miodrag Milanović
a08fff9c0f
Merge pull request #3193 from YosysHQ/micko/verific_f 
Add ability to override verilog mode for verific -f  command
 2022-02-09 12:41:26 +01:00
Miodrag Milanovic
2cef48bf2c Add ability to override verilog mode for verific -f command 2022-02-09 09:19:25 +01:00
Marcelina Kościelnicka
f61f2a4078 gowin: Fix LUT RAM inference, add more models. 2022-02-09 09:04:34 +01:00
Marcelina Kościelnicka
ac2bb70b52 ecp5: Fix DPR16X4 sim model. 2022-02-09 09:02:13 +01:00
github-actions[bot]
23d062fea3 Bump version 2022-02-08 00:59:03 +00:00
Miodrag Milanovic
818060880d Next dev cycle 2022-02-07 17:10:50 +01:00
Miodrag Milanovic
a4522d6282 Release version 0.14 2022-02-07 17:08:39 +01:00
Miodrag Milanovic
9647f6326f Update CHANGELOG and manual 2022-02-07 17:07:48 +01:00
Miodrag Milanović
d7f7227ce8
Merge pull request #3185 from YosysHQ/micko/co_sim 
Add co-simulation in sim pass
 2022-02-07 16:36:43 +01:00
github-actions[bot]
9c93668954 Bump version 2022-02-07 00:56:31 +00:00
Marcelina Kościelnicka
958c3a46ad nexus: Fix arith_map CO signal. 
Fixes #3187.
 2022-02-06 13:05:30 +01:00
Miodrag Milanovic
c0a156bcb4 Error detection for co-simulation 2022-02-04 11:11:36 +01:00
Miodrag Milanovic
6db23de7b1 bug fix and cleanups 2022-02-04 10:01:06 +01:00
github-actions[bot]
675a7bd22c Bump version 2022-02-03 00:54:22 +00:00
Miodrag Milanović
2d98fe870c
Merge pull request #3183 from YosysHQ/micko/nto1mux 
Use bmux for NTO1MUX
 2022-02-02 16:22:53 +01:00
Miodrag Milanovic
0b633b6c2e Use bmux for NTO1MUX 2022-02-02 16:16:08 +01:00
Miodrag Milanovic
7ef6da4c7d Add test cases for co-simulation 2022-02-02 13:22:44 +01:00
Miodrag Milanović
518521c72e
Merge pull request #3182 from yrabbit/wip-doc2 
Correct a typo in the manual
 2022-02-02 12:19:17 +01:00
YRabbit
f5609d52c4 Correct a typo in the manual 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-02-02 21:14:38 +10:00
Miodrag Milanovic
4a30c9cb94 Fix Visual Studio build 2022-02-02 11:46:06 +01:00
Miodrag Milanovic
990aee5531 respect hide_internal flag 2022-02-02 10:15:22 +01:00
Miodrag Milanovic
169ffcd2fb unify cycles counting and cleanup 2022-02-02 10:08:23 +01:00
Miodrag Milanovic
820b2fdd65 added stimulus mode and param check 2022-02-02 09:37:32 +01:00
Scott Thibault
0a6e2bd5d5 Update comment 2022-02-02 03:21:09 +01:00
Scott Thibault
e04ac4e9e9 Fix unextend method for signed constants 2022-02-02 03:21:09 +01:00
Miodrag Milanovic
8ba2000a50 error when no signal found 2022-01-31 17:41:50 +01:00
Miodrag Milanović
bf85dfee5e
Merge pull request #3176 from higuoxing/fix-ref-manual 
Fix the help message of synth_quicklogic command.
 2022-01-31 16:11:00 +01:00
Miodrag Milanovic
1b5ff92e62 Cleanup 2022-01-31 13:45:28 +01:00
Miodrag Milanovic
eabd0ff115 Compare bits when not all are defined 2022-01-31 13:41:02 +01:00
Miodrag Milanovic
26de52fa09 Cleanup 2022-01-31 12:00:15 +01:00
Miodrag Milanovic
6513300db7 message update 2022-01-31 11:41:52 +01:00
Miodrag Milanovic
543feb75cb Display simulation time data 2022-01-31 10:52:47 +01:00
Miodrag Milanovic
a6959d30df Use edges when explicit 2022-01-31 09:38:25 +01:00
Miodrag Milanovic
cbadfa0268 Updating initial state and checks 2022-01-31 09:19:34 +01:00
Miodrag Milanovic
190e44f0da Fix scope 2022-01-31 08:56:29 +01:00
github-actions[bot]
fc40df0916 Bump version 2022-01-31 00:54:31 +00:00
Marcelina Kościelnicka
56e7791760 verilog backend: Emit a wire for ports as well. 
Fixes #3177.
 2022-01-31 01:08:41 +01:00
Xing GUO
0520e99968 Fix the help message of synth_quicklogic. 2022-01-31 02:23:59 +08:00
Marcelina Kościelnicka
07a657fb0c opt_reduce: Add $bmux and $demux optimization patterns. 2022-01-30 03:37:52 +01:00