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verilog backend: Emit a wire for ports as well.

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Fixes #3177.
This commit is contained in:
Marcelina Kościelnicka 2022-01-30 20:48:50 +01:00
parent 07a657fb0c
commit 56e7791760
1 changed files with 1 additions and 1 deletions
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2
backends/verilog/verilog_backend.cc
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@ -432,7 +432,7 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
dump_const(f, wire->attributes.at(ID::init));
}
f << stringf(";\n");
} else if (!wire->port_input && !wire->port_output)
} else
f << stringf("%s" "wire%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
#endif
}