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									 Eddie Hung | 709f76c107 | Remove use of abc_box_id in stat | 2019-04-17 16:35:27 -07:00 |  | 
				
					
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									 Eddie Hung | 23cd2e5de0 | Fix $anyseq warning and cleanup | 2019-04-17 16:03:29 -07:00 |  | 
				
					
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									 Eddie Hung | 8fd455c910 | Update Makefile.inc too | 2019-04-17 15:19:48 -07:00 |  | 
				
					
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									 Eddie Hung | c795e14d25 | Reduce to three devices: hx, lp, u | 2019-04-17 15:19:02 -07:00 |  | 
				
					
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									 Eddie Hung | abcd3103ff | Do not print slack histogram | 2019-04-17 15:11:14 -07:00 |  | 
				
					
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									 Eddie Hung | 5c0853fc51 | Add up5k timings | 2019-04-17 15:10:39 -07:00 |  | 
				
					
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									 Eddie Hung | 4b520ae627 | Fix grammar | 2019-04-17 15:10:22 -07:00 |  | 
				
					
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									 Eddie Hung | 3105a8a653 | Update error message | 2019-04-17 15:07:44 -07:00 |  | 
				
					
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									 Eddie Hung | 6f3e5297db | Add "-device" argument to synth_ice40 | 2019-04-17 15:04:46 -07:00 |  | 
				
					
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									 Eddie Hung | 671cca59a9 | Missing abc_flop_q attribute on SPRAM | 2019-04-17 14:44:08 -07:00 |  | 
				
					
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									 Eddie Hung | 1ec5f18346 | Cope with inout ports | 2019-04-17 14:43:45 -07:00 |  | 
				
					
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									 Eddie Hung | 437fec0d88 | Map to SB_LUT4 from fastest input first | 2019-04-17 13:01:17 -07:00 |  | 
				
					
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									 Eddie Hung | fd89c1056e | Working ABC9 script | 2019-04-17 12:33:32 -07:00 |  | 
				
					
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									 Eddie Hung | 2b860809e9 | Stop topological sort at abc_flop_q | 2019-04-17 12:28:19 -07:00 |  | 
				
					
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									 Eddie Hung | 58847df1b9 | Mark seq output ports with "abc_flop_q" attr | 2019-04-17 12:27:45 -07:00 |  | 
				
					
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									 Eddie Hung | 1eade06671 | Also update Makefile.inc | 2019-04-17 12:27:02 -07:00 |  | 
				
					
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									 Eddie Hung | 4fb9ccfcd8 | synth_ice40 to use renamed files | 2019-04-17 12:22:03 -07:00 |  | 
				
					
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									 Eddie Hung | 42c33db22c | Rename to abc.* | 2019-04-17 12:15:34 -07:00 |  | 
				
					
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									 Eddie Hung | c1ebe51a75 | Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues" This reverts commit a7632ab332. | 2019-04-17 11:10:20 -07:00 |  | 
				
					
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									 Eddie Hung | a7632ab332 | Try using an ICE40_CARRY_LUT primitive to avoid ABC issues | 2019-04-17 11:10:04 -07:00 |  | 
				
					
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									 Eddie Hung | d59185f1d6 | Remove init* from xaiger, also topo-sort cells for box flow | 2019-04-17 11:08:42 -07:00 |  | 
				
					
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									 Eddie Hung | 116176e151 | Merge remote-tracking branch 'origin/master' into xaig | 2019-04-17 11:01:15 -07:00 |  | 
				
					
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									 Eddie Hung | e1b550d203 | Ignore a/i/o/h XAIGER extensions | 2019-04-17 10:55:23 -07:00 |  | 
				
					
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									 Eddie Hung | 17fb6c3522 | Fix spacing | 2019-04-17 08:40:50 -07:00 |  | 
				
					
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									 Clifford Wolf | ea8ac0aaad | Update to ABC d1b6413 Signed-off-by: Clifford Wolf <clifford@clifford.at> | 2019-04-17 13:51:34 +02:00 |  | 
				
					
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									 Eddie Hung | 5c134980c4 | Optimise | 2019-04-16 21:05:44 -07:00 |  | 
				
					
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									 Eddie Hung | 743c164eee | Add SB_LUT4 to box library | 2019-04-16 17:34:11 -07:00 |  | 
				
					
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									 Eddie Hung | 7980118d74 | Add ice40 box files | 2019-04-16 16:39:30 -07:00 |  | 
				
					
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									 Eddie Hung | ae2653c50f | abc9 to output some more info | 2019-04-16 16:39:16 -07:00 |  | 
				
					
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									 Eddie Hung | e7a8955818 | CIs before PIs; also sort each cell's connections before iterating | 2019-04-16 16:37:47 -07:00 |  | 
				
					
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									 Eddie Hung | b015ed48f7 | Merge remote-tracking branch 'origin/master' into xaig | 2019-04-16 15:04:20 -07:00 |  | 
				
					
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									 Eddie Hung | 55a3638c71 | Port from xc7mux branch | 2019-04-16 15:01:45 -07:00 |  | 
				
					
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									 Eddie Hung | cbb85e40e8 | Add MUXCY and XORCY to cells_box.v | 2019-04-16 14:53:28 -07:00 |  | 
				
					
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									 Eddie Hung | ece5c3ab38 | Fix wire numbering | 2019-04-16 14:53:01 -07:00 |  | 
				
					
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									 Eddie Hung | 43cd047fb9 | Do not put constants into output_bits | 2019-04-16 13:44:15 -07:00 |  | 
				
					
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									 Eddie Hung | 61ca83e099 | Remove write_verilog call | 2019-04-16 13:24:54 -07:00 |  | 
				
					
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									 Eddie Hung | aece97024d | Fix spacing | 2019-04-16 13:16:20 -07:00 |  | 
				
					
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									 Eddie Hung | fc5fda595d | Merge branch 'xaig' into xc7mux | 2019-04-16 13:15:53 -07:00 |  | 
				
					
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									 Eddie Hung | 0c8a839f13 | Re-enable partsel.v test | 2019-04-16 13:10:35 -07:00 |  | 
				
					
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									 Eddie Hung | afcb86c3d1 | abc9 to call "setundef -zero" behaving as for abc | 2019-04-16 13:10:13 -07:00 |  | 
				
					
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									 Eddie Hung | fed1f0ba63 | NULL check before use | 2019-04-16 12:59:48 -07:00 |  | 
				
					
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									 Eddie Hung | f22aa4422d | WIP for box support | 2019-04-16 12:57:27 -07:00 |  | 
				
					
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									 Eddie Hung | 98c297fabf | ABC to read_box before reading netlist | 2019-04-16 12:44:10 -07:00 |  | 
				
					
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									 Eddie Hung | 53b19ab1f5 | Make cells.box whiteboxes not blackboxes | 2019-04-16 12:43:14 -07:00 |  | 
				
					
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									 Eddie Hung | 5189695362 | read_verilog cells_box.v before techmap | 2019-04-16 12:41:56 -07:00 |  | 
				
					
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									 Eddie Hung | 2df7d97b72 | Merge pull request #939 from YosysHQ/revert895 Revert #895 (mux-to-shiftx optimisation) | 2019-04-16 11:59:21 -07:00 |  | 
				
					
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									 Eddie Hung | d259e6dc14 | synth_xilinx: before abc read +/xilinx/cells_box.v | 2019-04-16 11:21:46 -07:00 |  | 
				
					
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									 Eddie Hung | 3ac4977b70 | Add +/xilinx/cells_box.v containing models for ABC boxes | 2019-04-16 11:21:03 -07:00 |  | 
				
					
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									 Eddie Hung | b89bb74452 | For 'stat' do not count modules with abc_box_id | 2019-04-16 11:19:54 -07:00 |  | 
				
					
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									 Eddie Hung | a2b106135b | Do not call abc on modules with abc_box_id attr | 2019-04-16 11:19:42 -07:00 |  |