Akash Levy
623c54d513
Only do SFCU if has VHDL
2025-10-02 06:02:39 -07:00
Akash Levy
6021168b03
Add back VHDL support
2025-10-02 00:39:33 -07:00
Akash Levy
aa16191b80
Merge branch 'YosysHQ:main' into main
2025-10-01 22:22:07 -07:00
Akash Levy
a353716202
Update fanoutbuf
2025-10-01 20:59:36 -07:00
Akash Levy
66abd04b5a
Remove annotate_logic_depth
2025-10-01 20:57:51 -07:00
Akash Levy
c8d8c4f408
Add fanoutbuf pass
2025-10-01 19:23:45 -07:00
Akash Levy
17e3ed3258
Remove annotate_unqcoef (for now)
2025-10-01 19:23:13 -07:00
github-actions[bot]
f7120e9c2a
Bump version
2025-10-02 00:22:09 +00:00
Jannis Harder
058766da22
Merge pull request #5393 from sifferman/ifdef_tran
...
Added ifndef SIMLIB_NOCONNECT
2025-10-01 21:05:44 +02:00
Ethan Sifferman
d5beb65d30
added SIMLIB_VERILATOR_COMPAT
2025-10-01 10:19:25 -07:00
Emil J
2872847ea5
Merge pull request #5403 from rocallahan/idstring-empty
...
Optimize `IdString::empty()`
2025-10-01 11:23:59 +02:00
Robert O'Callahan
d45223976a
Optimize IdString::empty()
...
I actually saw this take 0.6% of the time in an `opt_clean` pass (under Module::check()).
Trivial issue, but the fix is also trivial and simple.
2025-10-01 02:49:03 +00:00
github-actions[bot]
01eaaa4b90
Bump version
2025-10-01 00:26:18 +00:00
Akash Levy
40f562475e
Smallfix
2025-09-30 14:18:23 -07:00
Akash Levy
dee059bee8
Fix minor Yosys issues
2025-09-30 12:05:36 -07:00
Akash Levy
c26f38faeb
Merge branch 'YosysHQ:main' into main
2025-09-30 11:14:33 -07:00
Emil J
7719beb4ae
Merge pull request #5349 from rocallahan/cleanup-hashops
...
Reduce hashops verbiage in `OptMergePass`
2025-09-30 19:34:44 +02:00
Emil J
60c551f961
Merge pull request #5400 from YosysHQ/emil/github-contribution-template-update
...
Update contribution templates
2025-09-30 11:03:49 +02:00
Emil J. Tywoniak
dc7764e247
.github: typos
2025-09-30 11:03:19 +02:00
Miodrag Milanović
330a5fc101
Merge pull request #5402 from YosysHQ/micko/extensions
...
Force linking log_compat when extensions are linked
2025-09-30 09:10:04 +02:00
Miodrag Milanovic
e6fa0223c8
Force linking log_compat when extensions are linked
2025-09-30 08:44:31 +02:00
Akash Levy
16215b8786
Merge upstream
2025-09-29 20:58:56 -07:00
Akash Levy
93a24fe275
Put back is_mostly_const
2025-09-29 20:56:58 -07:00
Akash Levy
313c7e4b95
Fix wreduce using queueing algorithm
2025-09-29 20:28:55 -07:00
github-actions[bot]
5fd2aecd90
Bump version
2025-09-30 00:23:05 +00:00
Emil J. Tywoniak
b86cc0d9b3
docs: replace Slack with Discourse in extensions writing guide
2025-09-29 23:20:06 +02:00
Emil J. Tywoniak
b2adaeec69
.github: replace Slack and GitHub Discussions with Discourse in issue templates
2025-09-29 23:03:54 +02:00
Emil J. Tywoniak
4c17ac5ac2
.github: suggest Discourse in PR template
2025-09-29 23:03:29 +02:00
Akash Levy
d36bc8231f
Revert wreduce to initial state
2025-09-29 12:44:30 -07:00
ShinyKate
30cb72a162
Merge pull request #4125 from povik/read-blif-gate-ff
...
read_blif: Represent sequential elements with gate cells
2025-09-29 08:21:16 -05:00
Jannis Harder
47639f8a98
Merge pull request #5388 from jix/bufnorm-followup
...
Refactor and fixes to incremental bufNormalize + related changes
2025-09-29 15:15:29 +02:00
Jannis Harder
6a7372626a
Merge pull request #5389 from jix/sva_continue
...
verific: New `-sva-continue-on-error` import option
2025-09-29 15:07:54 +02:00
Emil J
87c1a868d3
Merge pull request #5384 from rocallahan/simplify-opt-merge-logic
...
Move `OptMerge` cell filtering logic to happen while building the cell vector
2025-09-29 15:03:01 +02:00
Martin Povišer
04c7013f0e
Merge pull request #5399 from povik/opt_hier-bug
...
opt_hier: Fix two optimizations conflicting
2025-09-29 14:53:54 +02:00
Akash Levy
ded986c510
Probably not fast but it works
2025-09-29 04:39:07 -07:00
Akash Levy
b2f2d6d6e3
Actually fix wreduce
2025-09-29 04:16:18 -07:00
Akash Levy
acf3a6606f
Small gitignore fixes
2025-09-29 12:11:59 +01:00
Akash Levy
dfc8607a77
Fixups
2025-09-29 03:49:44 -07:00
Martin Povišer
a9318db2fa
opt_hier: Adjust messages
2025-09-29 12:27:27 +02:00
Martin Povišer
ffe2f7a16d
opt_hier: Fix two optimizations conflicting
...
Fix a conflict between the following two:
* propagation of tied-together inputs in
* propagation of unused inputs out
2025-09-29 12:27:27 +02:00
Akash Levy
5bf99ac85b
Merge branch 'YosysHQ:main' into main
2025-09-29 02:31:20 -07:00
Miodrag Milanović
69770a844e
Merge pull request #5396 from akashlevy/pyosys_fix
...
BUGFIX: pyosys cannot parse header with omitted function args
2025-09-29 10:20:31 +02:00
Akash Levy
fbc2b71ed4
Revert some stuff
2025-09-29 00:43:49 -07:00
Akash Levy
0b0c7bd19d
Fix wreduce speed issue
2025-09-29 00:18:48 -07:00
Akash Levy
b5f3d7ee9c
Revert three passes
2025-09-29 00:18:34 -07:00
Jannis Harder
86fb2f16f7
bufnorm: Refactor and fix incremental bufNormalize
...
This fixes some edge cases the previous version didn't handle properly
by simplifying the logic of determining directly driven wires and
representatives to use as buffer inputs.
2025-09-29 08:21:28 +02:00
Jannis Harder
cbc1055517
opt_clean: Fix debug output when cleaning up bufnorm cells
2025-09-29 08:21:28 +02:00
Jannis Harder
90669ab4eb
aiger2: Only fail for reachable undirected bufnorm helper cells
...
The aiger2 backend checks for unsupported cells during indexing. This
causes it to fail when `$connect` or `$tribuf` (as workaround for
missing 'z-$buf support) cells are present in the module.
Since bufnorm adds these cells automatically, it is very easy to end up
with them due to unconnected wires or e.g. `$specify` cells, which do
not pose an actual problem for the backend, since it will never
encounter those during a traversal.
With this, we ignore them during indexing and only produce an actual error
message if we reach such a cell during the traversal.
2025-09-29 08:21:28 +02:00
Jannis Harder
9396e5e5fe
portarcs: Ignore all bufnorm helper cells
...
The `portarcs` pass was already ignoring `$buf` cells when loading
timing data, but now bufnorm will also emit `$input_port` and `$connect`
helper cells, which need to be ignored as well.
2025-09-29 08:21:28 +02:00
Akash Levy
a0d1c8b30f
More minor cleanup
2025-09-28 07:19:53 -07:00
