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Author SHA1 Message Date
YRabbit
a1dd794ff8 gowin: Add all the primitives. 
Use selected data (names, ports and parameters) from vendor file for
GW1N series primitives.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-04-22 17:10:53 +10:00
Jannis Harder
3cbca5064c verific: Handle non-seq properties with VerificClocking conditions 2023-04-21 17:19:42 +02:00
Jannis Harder
ec47bf1745 verific: Handle conditions when using sva_at_only in VerificClocking 
This handles conditions on clocked concurrent assertions in unclocked
procedural contexts.
 2023-04-21 16:51:42 +02:00
Jannis Harder
985f4926b7 verilog: Fix const eval of unbased unsized constants 
When the verilog frontend perfomed constant evaluation of unbased
unsized constants in a context-determined expression it did not properly
extend them by repeating the bit value. This only affected constant
evaluation and not constants that made it through unchanged to RTLIL.
The latter case was already covered by tests and working before.

This fixes the const-eval issue by checking the `is_unsized` flag in
bitsAsConst and extending the value accordingly.

The newly added test also tests the already working non-const-eval case
to highlight that both cases should behave the same.
 2023-04-20 12:12:50 +02:00
AdamHillier
3861cc31f0 Add outputs before inputs to the sigmap in the AIGER backend. 2023-04-19 11:00:51 +00:00
github-actions[bot]
7efc50367e Bump version 2023-04-19 00:16:35 +00:00
Jannis Harder
88ae463ffe
Merge pull request #3732 from hzeller/20230417-remote-statement-no-effect 
Remove a statement without effect.
 2023-04-18 10:45:14 +02:00
Henner Zeller
a3a8f7be38 Remove a statement without effect. 
The return value of the min(...) call is never used.
Looks like some leftover from some previous implementation.

Signed-off-by: Henner Zeller <h.zeller@acm.org>
 2023-04-17 10:53:05 -07:00
github-actions[bot]
a9c792dcee Bump version 2023-04-15 00:16:41 +00:00
Miodrag Milanovic
d0855576ae Next dev cycle 2023-04-14 09:54:46 +02:00
Miodrag Milanovic
0d6f4b0683 Release version 0.28 2023-04-14 09:52:15 +02:00
Miodrag Milanović
b377a39b73
Merge pull request #3727 from YosysHQ/micko/pll_bram 
MachXO2: Add PLL and EBR related primitives
 2023-04-14 09:34:30 +02:00
github-actions[bot]
a2655a4b70 Bump version 2023-04-13 00:14:37 +00:00
gatecat
e56dad56c4 fabulous: Add support for LUT6s 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-04-12 18:42:09 +02:00
YRabbit
f9a6c0fcbd gowin: Add serialization/deserialization primitives 
Primitives are added to convert parallel signals to serial and vice versa.

IDES4, IDES8, IDES10, IDES16, IVIDEO, OSER4, OSER8, OSER10, OSER16, OVIDEO.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-04-12 09:59:57 +01:00
Miodrag Milanovic
ee3162c58d Add PLL and EBR related primitives 2023-04-10 12:39:09 +02:00
github-actions[bot]
101075611f Bump version 2023-04-07 00:14:38 +00:00
gatecat
266f81816b ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB model 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-04-06 10:18:48 +01:00
Miodrag Milanovic
0f5e7c244d add additional dff and lutram tests 2023-04-06 09:10:14 +02:00
Miodrag Milanovic
54d313efc3 add test for CCU2D 2023-04-06 09:10:14 +02:00
Miodrag Milanovic
9e9fae1966 Add more DFF types 2023-04-06 09:10:14 +02:00
Miodrag Milanovic
d5a405d3b4 Added proper simulation model for CCU2D 2023-04-06 09:10:14 +02:00
Miodrag Milanovic
6e4c1675e7 Generate TRELLIS_DPR16X4 for lutram 2023-04-06 09:10:14 +02:00
Miodrag Milanovic
6e12da3956 machxo2: Initial support for carry chains (CCU2D) 2023-04-06 09:10:14 +02:00
Martin Povišer
bd06338172 py_wrap_generator: Fix handling of method name collisions 
If two methods have the same signature but for qualifiers the Python
binding doesn't care about ('const'), do not generate a mangled name for
the method.

Fixes

    .def<Wire (Module::*)(const IdString* )>("wire__YOSYS_NAMESPACE_RTLIL_IdString", &Module::wire__YOSYS_NAMESPACE_RTLIL_IdString)
    .def<Cell (Module::*)(const IdString* )>("cell__YOSYS_NAMESPACE_RTLIL_IdString", &Module::cell__YOSYS_NAMESPACE_RTLIL_IdString)

in the output after the previous change.
 2023-04-05 13:36:44 +02:00
Martin Povišer
f94f544b50 Fix the python generator for a bunch of const cases 
Makes the below show up in the binding.

    .def<const char * (IdString::*)(void)>("c_str", &IdString::c_str)

    .def<boost::python::list (SigSpec::*)(void)>("chunks", &SigSpec::chunks)
    .def<boost::python::list (SigSpec::*)(void)>("bits", &SigSpec::bits)
    .def<SigBit (SigSpec::*)(int, const SigBit* )>("at", &SigSpec::at)

    .def<SigSpec (Cell::*)(const IdString* )>("getPort", &Cell::getPort)
    .def<boost::python::dict (Cell::*)(void)>("connections", &Cell::connections)
    .def<Const (Cell::*)(const IdString* )>("getParam", &Cell::getParam)

    .def<boost::python::list (Module::*)(void)>("connections", &Module::connections)

    def<const char * (*)(const SigSpec* )>("log_signal", YOSYS_PYTHON::log_signal);
    def<const char * (*)(const SigSpec* , bool)>("log_signal", YOSYS_PYTHON::log_signal);
    def<const char * (*)(const Const* )>("log_const", YOSYS_PYTHON::log_const);
    def<const char * (*)(const Const* , bool)>("log_const", YOSYS_PYTHON::log_const);
    def<const char * (*)(const IdString* )>("log_id", YOSYS_PYTHON::log_id);
 2023-04-05 13:36:44 +02:00
github-actions[bot]
53c0a6b780 Bump version 2023-03-24 00:16:02 +00:00
Miodrag Milanovic
f35bdaa527 Update Xilinx cell definitions, fixes #3699 2023-03-23 09:44:36 +01:00
github-actions[bot]
23826e5152 Bump version 2023-03-21 00:15:46 +00:00
Jannis Harder
dc0a799c06
Merge pull request #3708 from jix/void_func 
verilog: Support void functions
 2023-03-20 16:10:19 +01:00
Jannis Harder
fb1c2be76b verilog: Support void functions 
The difference between void functions and tasks is that always_comb's
implicit sensitivity list behaves as if functions were inlined, but
ignores signals read only in tasks. This only matters for event based
simulation, and for synthesis we can treat a void function like a task.
 2023-03-20 12:52:46 +01:00
Miodrag Milanovic
61da330a38 Update tests 2023-03-20 09:58:41 +01:00
Miodrag Milanovic
ff9f1fb86e Start unification effort for machxo2 and ecp5 2023-03-20 09:58:41 +01:00
Miodrag Milanovic
4d7e9e2e5d Add additional iopad_external_pin attributes 2023-03-20 09:17:22 +01:00
Miodrag Milanovic
db367bd69e Add iopad_external_pin to some basic io primitives 2023-03-20 09:17:22 +01:00
Miodrag Milanovic
10589c57bf insert IO buffers for ECP5, off by default 2023-03-20 09:17:22 +01:00
github-actions[bot]
ceef00c35e Bump version 2023-03-16 00:17:57 +00:00
Miodrag Milanović
57fb1f51b2
Merge pull request #3704 from jix/enum_values 
verific: Fix enum_values support and signed attribute values
 2023-03-15 10:54:19 +01:00
Jannis Harder
390d1c583a verific: Fix enum_values support and signed attribute values 
This uses the same constant parsing for enum_values and for attributes
and extends it to handle signed values as those are used for enums that
implicitly use the int type.
 2023-03-15 09:51:36 +01:00
github-actions[bot]
101d19bb6a Bump version 2023-03-11 00:15:30 +00:00
Jannis Harder
c50f641812
Merge pull request #3682 from daglem/struct-member-out-of-bounds 
Out of bounds checking for struct/union members
 2023-03-10 16:14:56 +01:00
Stefan Riesenberger
baa3659ea5 ice40: Fix path delay definitions 
Parallel connections do not allow matching different bit widths.
A full connection has to be used instead.
Allows iverilog to parse the simulation library with hardware path delays enabled.
 2023-03-10 10:48:05 +01:00
Dag Lem
1af7d6121f Added test for dynamic indexing within struct members 2023-03-08 20:25:39 +01:00
github-actions[bot]
b58664d441 Bump version 2023-03-07 00:18:51 +00:00
N. Engelhardt
7c5ae560a8
Merge pull request #3684 from YosysHQ/fix-GIT_REV 2023-03-06 16:12:36 +01:00
Miodrag Milanovic
368f2984cd Next dev cycle 2023-03-06 08:50:14 +01:00
Miodrag Milanovic
5f88c218b5 Release version 0.27 2023-03-06 08:47:51 +01:00
Dag Lem
0d3423ddea Index struct/union members within corresponding wire chunks 
This guards against access to bits outside of struct/union
members via dynamic indexing.
 2023-03-05 14:54:17 +01:00
github-actions[bot]
9747e55d95 Bump version 2023-03-02 00:18:47 +00:00
Catherine
3f173c2180 Makefile: fix GIT_REV extraction if Yosys is built as submodule. 2023-03-01 21:17:19 +00:00