9832 commits

This branch

This branch

All branches

Author	SHA1	Message	Date
Eddie Hung	07eecff9cc	Merge pull request #2055 from YosysHQ/eddie/logger_multiple ... logger: fix for multiple calls with same pattern	2020-05-14 15:30:08 -07:00
Alberto Gonzalez	976edb7597	kernel: Ensure dict always hashes to the same value given the same contents.	2020-05-14 20:06:55 +00:00
Alberto Gonzalez	35b94d1f66	kernel: Re-implement dict hash code as a dict member function instead of a specialized template for hash_ops.	2020-05-14 20:06:55 +00:00
Alberto Gonzalez	e173291649	techmap: Replace naughty const_cast<>()s. ... Co-Authored-By: Eddie Hung <eddie@fpgeh.com>	2020-05-14 20:06:55 +00:00
Alberto Gonzalez	97fd304cbe	techmap: Replace pseudo-private member usage with the range accessor function and some naughty const_cast<>()s.	2020-05-14 20:06:55 +00:00
Eddie Hung	36bb201dd9	techmap: sort celltypeMap as it determines techmap order	2020-05-14 20:06:55 +00:00
Alberto Gonzalez	ce62d0751a	Replace std::sets using custom comparators with pool. ... Co-Authored-By: Eddie Hung <eddie@fpgeh.com>	2020-05-14 20:06:55 +00:00
Eddie Hung	dabeb1e8a1	techmap: prefix special wires with backslash for use as IdString	2020-05-14 20:06:55 +00:00
Alberto Gonzalez	bd54d67ad4	Further clean up passes/techmap/techmap.cc. ... Co-Authored-By: Eddie Hung <eddie@fpgeh.com>	2020-05-14 20:06:54 +00:00
Alberto Gonzalez	982562ff13	Use emplace() for more efficient insertion into various dicts.	2020-05-14 20:06:54 +00:00
Alberto Gonzalez	c658d9d59d	Build constant bits directly rather than constructing an object and copying its bits.	2020-05-14 20:06:54 +00:00
Alberto Gonzalez	f235f212ea	Replace std::set with pool for cell_to_inbit and outbit_to_cell.	2020-05-14 20:06:54 +00:00
Alberto Gonzalez	6294621825	Use emplace() rather than insert().	2020-05-14 20:06:54 +00:00
Alberto Gonzalez	dfcb936cd5	Clean up pseudo-private member usage and ensure range iteration uses references where possible to avoid unnecessary copies.	2020-05-14 20:06:54 +00:00
Alberto Gonzalez	a4755c50c3	Clean up extraneous buffer.	2020-05-14 20:06:54 +00:00
Alberto Gonzalez	7857782575	Replace std::map with dict for unique_bit_id.	2020-05-14 20:06:54 +00:00
Alberto Gonzalez	6d64d768b0	Replace std::map with dict for port_new2old_map, port_connmap, and cellbits_to_tplbits.	2020-05-14 20:06:54 +00:00
Alberto Gonzalez	5cb4ae4666	Replace std::map with dict for connbits_map, cell_to_inbit, and outbit_to_cell.	2020-05-14 20:06:54 +00:00
Alberto Gonzalez	c43017fc08	Replace std::map with dict for TechmapWires type.	2020-05-14 20:06:54 +00:00
Alberto Gonzalez	644e55b3d3	Replace std::map with dict for celltypeMap.	2020-05-14 20:06:53 +00:00
Alberto Gonzalez	67f4046c05	Replace std::set with pool for handled_cells and techmap_wire_names.	2020-05-14 20:06:53 +00:00
Alberto Gonzalez	64c16f8c13	Replace std::map with dict for positional_ports.	2020-05-14 20:06:53 +00:00
Alberto Gonzalez	2fb4931e5b	Add specialized hash() for type dict and use a dict instead of a std::map for techmap_cache and techmap_do_cache.	2020-05-14 20:06:53 +00:00
Alberto Gonzalez	437f3fb342	Replace std::map with dict for simplemap_mappers.	2020-05-14 20:06:53 +00:00
Alberto Gonzalez	99b586b283	Use nullptr instead of NULL in passes/techmap/techmap.cc.	2020-05-14 20:06:53 +00:00
Alberto Gonzalez	5f7f213c7f	Replace std::string and RTLIL::IdString with IdString in passes/techmap/techmap.cc. ... Co-Authored-By: Eddie Hung <eddie@fpgeh.com>	2020-05-14 20:06:53 +00:00
Alberto Gonzalez	e49fdee404	Do not modify design modules while iterating over modules(). ... Co-Authored-By: Eddie Hung <eddie@fpgeh.com>	2020-05-14 20:06:53 +00:00
Alberto Gonzalez	985a29ff3b	Clean up pseudo-private member usage, superfluous std::vector instantiation, and RTLIL::id2cstr() usage in passes/techmap/techmap.cc.	2020-05-14 20:06:53 +00:00
Eddie Hung	7b3a4a1fff	opt_expr: Sx to Sz; spotted by @Xiretza	2020-05-14 12:14:23 -07:00
Eddie Hung	73b7ea713c	Merge pull request #1994 from YosysHQ/eddie/fix_bug1758 ... opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too	2020-05-14 11:56:22 -07:00
Eddie Hung	425867d175	logger: clean up doc	2020-05-14 10:38:31 -07:00
Eddie Hung	02df0198b6	abc9_ops: -prep_hier to create unmap module that removes Q's (* init *)	2020-05-14 10:33:57 -07:00
Eddie Hung	13f9d65b6f	abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it	2020-05-14 10:33:57 -07:00
Eddie Hung	fa31e84112	Fix broken test when ignoring abc9_flop with init == 1'b1	2020-05-14 10:33:57 -07:00
Eddie Hung	97a0a04314	abc9_ops/xaiger: further reducing Module::derive() calls by ... ... replacing _all_ (* abc9_box *) instantiations with their derived types	2020-05-14 10:33:57 -07:00
Eddie Hung	e79127fceb	Cleanup; reduce Module::derive() calls	2020-05-14 10:33:57 -07:00
Eddie Hung	cea614f5ae	ecp5: latches_map.v if *not* -asyncprld	2020-05-14 10:33:57 -07:00
Eddie Hung	fdc340db8e	ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.v	2020-05-14 10:33:57 -07:00
Eddie Hung	39759d5f0e	ecp5: fix rebase mistake	2020-05-14 10:33:57 -07:00
Eddie Hung	8d34aee3d5	abc9: update to =_$abc9_flops pattern which includes whiteboxes	2020-05-14 10:33:57 -07:00
Eddie Hung	f652a9c11c	abc9_ops: update docs	2020-05-14 10:33:57 -07:00
Eddie Hung	ca4f8c9444	xilinx: gate specify/attributes from iverilog	2020-05-14 10:33:57 -07:00
Eddie Hung	57c478c537	abc9: only do +/abc9_map if `DFF	2020-05-14 10:33:57 -07:00
Eddie Hung	2946bb60e9	abc9: rework submod -- since it won't move (* keep *) cells	2020-05-14 10:33:56 -07:00
Eddie Hung	8cda29137e	ecp5: TRELLIS_FF bypass path only in async mode	2020-05-14 10:33:56 -07:00
Eddie Hung	7146c0339e	timinginfo: ignore $specify2 cells if EN is false	2020-05-14 10:33:56 -07:00
Eddie Hung	6c34945371	xilinx/ice40/ecp5: zinit requires selected wires, so select them all	2020-05-14 10:33:56 -07:00
Eddie Hung	b65610fb62	abc9_ops: move assert	2020-05-14 10:33:56 -07:00
Eddie Hung	ed7cb0b095	abc9: put 'aigmap' back	2020-05-14 10:33:56 -07:00
Eddie Hung	a323881e15	xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells	2020-05-14 10:33:56 -07:00