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Code Activity
8815 commits 122 branches 59 tags 72 MiB
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2914 commits

Author SHA1 Message Date
Clifford Wolf
0d2923cccd Connections between inputs and inouts are driven by the input 2016-04-26 19:49:05 +02:00
Clifford Wolf
958fb29c76 Fixed test_autotb for modules with many cell ports 2016-04-25 16:37:11 +02:00
Clifford Wolf
93e107e455 Fixed proc_mux performance bug 2016-04-25 10:43:04 +02:00
Clifford Wolf
b1d6f05fa2 Fixed performance bug in proc_dlatch 2016-04-24 19:29:56 +02:00
Clifford Wolf
096c25d29d Improvements in greenpak4 shreg mapping 2016-04-23 23:10:13 +02:00
Andrew Zonenberg
7f16784f3c Merge https://github.com/cliffordwolf/yosys 2016-04-23 12:22:08 -07:00
Clifford Wolf
e13c66122e Added "shregmap -zinit" for greenpak4 tech 2016-04-23 20:20:21 +02:00
Andrew Zonenberg
2849fd486e Fixed typo in help text 2016-04-22 23:01:39 -07:00
Clifford Wolf
7311be4028 Added "shregmap -tech greenpak4" 2016-04-22 19:42:08 +02:00
Clifford Wolf
965b0d59b5 More flexible handling of initialization values 2016-04-22 12:13:06 +02:00
Clifford Wolf
0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf
1565d1af69 Fixed performance bug in "share" pass 2016-04-21 19:47:25 +02:00
Clifford Wolf
f38ca3e18f Improvements in opt_expr 2016-04-21 14:23:04 +02:00
Clifford Wolf
1761d08dd2 Bugfix and improvements in memory_share 2016-04-21 14:22:58 +02:00
Clifford Wolf
f1fa757d0e Added "shregmap -params" 2016-04-18 11:58:21 +02:00
Clifford Wolf
525651c8f6 Added "shregmap -zinit" and "shregmap -init" 2016-04-18 11:44:10 +02:00
Clifford Wolf
ce7c980ec7 Improvements in "shregmap" 2016-04-17 15:37:22 +02:00
Clifford Wolf
de647a390c Added "shregmap" pass 2016-04-16 23:20:49 +02:00
Clifford Wolf
fbdb8e7b3e Fixed copy&paste error in log message in lut2mux 2016-04-16 23:20:34 +02:00
Clifford Wolf
6041f780c3 Prefer noninverting FFs in dfflibmap 2016-04-05 12:51:04 +02:00
Clifford Wolf
eaac5bfbc7 Improved formatting of "sat" output tables 2016-04-05 08:26:10 +02:00
Clifford Wolf
6cafd08ac1 Improved opt_merge support for $pmux cells 2016-03-31 09:58:55 +02:00
Clifford Wolf
e5dd5c0bcc Preserve empty $pmux default cases 2016-03-31 09:57:23 +02:00
Clifford Wolf
e2f6d61c00 Typo fixes in opt_expr and opt_merge 2016-03-31 09:56:56 +02:00
Clifford Wolf
ec93680bd5 Renamed opt_share to opt_merge 2016-03-31 08:52:49 +02:00
Clifford Wolf
1d0f0d668a Renamed opt_const to opt_expr 2016-03-31 08:46:56 +02:00
Andrew Zonenberg
984561c034 Renamed counters pass to greenpak4_counters 2016-03-30 22:52:01 -07:00
Andrew Zonenberg
1ae33344f4 Added initial implementation of "counters" pass to synth_greenpak4. Can only infer non-resettable down counters for now. 2016-03-30 22:40:14 -07:00
Andrew Zonenberg
1b42e0c471 Reduced log verbosity 2016-03-30 22:03:50 -07:00
Andrew Zonenberg
ad19e0c64a Continued work on counter extraction. Can recognize compatible RTL counters but not replace with hard macros. 2016-03-30 21:54:23 -07:00
Andrew Zonenberg
d16d05e415 Merge https://github.com/cliffordwolf/yosys 2016-03-30 20:38:18 -07:00
Andrew Zonenberg
dd7204c0bd Fixed typo in log message 2016-03-30 20:30:03 -07:00
Andrew Zonenberg
489caf32c5 Initial work on greenpak4 counter extraction. Doesn't work but a decent start 2016-03-30 01:07:20 -07:00
Clifford Wolf
a47f69536a Added support for installed plugins 2016-03-30 10:02:03 +02:00
Clifford Wolf
9717495401 Fixed handling of inverters (aka 1-input luts) in nlutmap 2016-03-23 08:56:08 +01:00
Clifford Wolf
043fa0fad0 Cleanup abstract modules at end of "hierarchy -top" 2016-03-21 16:37:35 +01:00
Clifford Wolf
2c7e107d7a Support for abstract modules in chparam 2016-03-21 16:37:35 +01:00
Clifford Wolf
bb9374b67c Improvements in ABCEXTERNAL handling 2016-03-19 20:02:40 +01:00
Sergey Kvachonok
2656b2c55a Support calling out to an external ABC. 
$ make ABCEXTERNAL=my-abc && make ABCEXTERNAL=my-abc install

configures yosys to use an external ABC executable instead of
building and installing the in-tree ABC copy (yosys-abc).
 2016-03-19 18:36:18 +03:00
Clifford Wolf
c4aaed099f Using "mfs" and "lutpack" in ABC lut mapping 2016-03-07 11:14:11 +01:00
Clifford Wolf
bcc873b805 Fixed some visual studio warnings 2016-02-13 17:31:24 +01:00
Clifford Wolf
0d7fd2585e Added "int ceil_log2(int)" function 2016-02-13 16:52:16 +01:00
Clifford Wolf
825b99efc1 Added "stat -liberty" for calculating chip area 2016-02-04 12:26:13 +01:00
Clifford Wolf
801c022457 Improved dffsr2dff pass 2016-02-02 19:42:49 +01:00
Clifford Wolf
d69395ca08 Added dffsr2dff 2016-02-02 17:19:01 +01:00
Clifford Wolf
d6592d5b99 Use alphanumerical order instead of idstring idx in opt_clean compare_signals() 2016-02-02 09:16:18 +01:00
Clifford Wolf
17372d8abd Added "abc -luts" option, Improved Xilinx logic mapping 2016-02-01 12:40:32 +01:00
Clifford Wolf
9251553592 Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs) 2016-02-01 11:49:11 +01:00
Clifford Wolf
71f418c468 More clang sanitizer stuff 2016-01-31 19:55:48 +01:00
Clifford Wolf
8b3f8cd220 Added "equiv_struct -fwonly" 2016-01-08 10:59:16 +01:00