mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 00:55:32 +00:00
Code Activity

Renamed opt_share to opt_merge

Browse source
This commit is contained in:
Clifford Wolf 2016-03-31 08:52:49 +02:00
parent 1d0f0d668a
commit ec93680bd5
8 changed files with 28 additions and 28 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/memory/memory_share.cc
View file

@ -746,7 +746,7 @@ struct MemorySharePass : public Pass {
log("\n");
log("Note that in addition to the algorithms implemented in this pass, the $memrd\n");
log("and $memwr cells are also subject to generic resource sharing passes (and other\n");
log("optimizations) such as opt_share.\n");
log("optimizations) such as \"share\" and \"opt_merge\".\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {

2
passes/opt/Makefile.inc
View file

@ -1,6 +1,6 @@
OBJS += passes/opt/opt.o
OBJS += passes/opt/opt_share.o
OBJS += passes/opt/opt_merge.o
OBJS += passes/opt/opt_muxtree.o
OBJS += passes/opt/opt_reduce.o
OBJS += passes/opt/opt_rmdff.o

16
passes/opt/opt.cc
View file

@ -38,12 +38,12 @@ struct OptPass : public Pass {
log("passes in the following order:\n");
log("\n");
log(" opt_expr [-mux_undef] [-mux_bool] [-undriven] [-clkinv] [-fine] [-full] [-keepdc]\n");
log(" opt_share [-share_all] -nomux\n");
log(" opt_merge [-share_all] -nomux\n");
log("\n");
log(" do\n");
log(" opt_muxtree\n");
log(" opt_reduce [-fine] [-full]\n");
log(" opt_share [-share_all]\n");
log(" opt_merge [-share_all]\n");
log(" opt_rmdff\n");
log(" opt_clean [-purge]\n");
log(" opt_expr [-mux_undef] [-mux_bool] [-undriven] [-clkinv] [-fine] [-full] [-keepdc]\n");
@ -53,7 +53,7 @@ struct OptPass : public Pass {
log("\n");
log(" do\n");
log(" opt_expr [-mux_undef] [-mux_bool] [-undriven] [-clkinv] [-fine] [-full] [-keepdc]\n");
log(" opt_share [-share_all]\n");
log(" opt_merge [-share_all]\n");
log(" opt_rmdff\n");
log(" opt_clean [-purge]\n");
log(" while <changed design in opt_rmdff>\n");
@ -68,7 +68,7 @@ struct OptPass : public Pass {
std::string opt_clean_args;
std::string opt_expr_args;
std::string opt_reduce_args;
std::string opt_share_args;
std::string opt_merge_args;
bool fast_mode = false;
log_header("Executing OPT pass (performing simple optimizations).\n");
@ -111,7 +111,7 @@ struct OptPass : public Pass {
continue;
}
if (args[argidx] == "-share_all") {
opt_share_args += " -share_all";
opt_merge_args += " -share_all";
continue;
}
if (args[argidx] == "-fast") {
@ -126,7 +126,7 @@ struct OptPass : public Pass {
{
while (1) {
Pass::call(design, "opt_expr" + opt_expr_args);
Pass::call(design, "opt_share" + opt_share_args);
Pass::call(design, "opt_merge" + opt_merge_args);
design->scratchpad_unset("opt.did_something");
Pass::call(design, "opt_rmdff");
if (design->scratchpad_get_bool("opt.did_something") == false)
@ -139,12 +139,12 @@ struct OptPass : public Pass {
else
{
Pass::call(design, "opt_expr" + opt_expr_args);
Pass::call(design, "opt_share -nomux" + opt_share_args);
Pass::call(design, "opt_merge -nomux" + opt_merge_args);
while (1) {
design->scratchpad_unset("opt.did_something");
Pass::call(design, "opt_muxtree");
Pass::call(design, "opt_reduce" + opt_reduce_args);
Pass::call(design, "opt_share" + opt_share_args);
Pass::call(design, "opt_merge" + opt_merge_args);
Pass::call(design, "opt_rmdff");
Pass::call(design, "opt_clean" + opt_clean_args);
Pass::call(design, "opt_expr" + opt_expr_args);

18
passes/opt/opt_share.cc → passes/opt/opt_merge.cc
View file

@ -31,7 +31,7 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct OptShareWorker
struct OptMergeWorker
{
RTLIL::Design *design;
RTLIL::Module *module;
@ -212,14 +212,14 @@ struct OptShareWorker
}
struct CompareCells {
OptShareWorker *that;
CompareCells(OptShareWorker *that) : that(that) {}
OptMergeWorker *that;
CompareCells(OptMergeWorker *that) : that(that) {}
bool operator()(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2) const {
return that->compare_cells(cell1, cell2);
}
};
OptShareWorker(RTLIL::Design *design, RTLIL::Module *module, bool mode_nomux, bool mode_share_all) :
OptMergeWorker(RTLIL::Design *design, RTLIL::Module *module, bool mode_nomux, bool mode_share_all) :
design(design), module(module), assign_map(module), mode_share_all(mode_share_all)
{
total_count = 0;
@ -286,13 +286,13 @@ struct OptShareWorker
}
};
struct OptSharePass : public Pass {
OptSharePass() : Pass("opt_share", "consolidate identical cells") { }
struct OptMergePass : public Pass {
OptMergePass() : Pass("opt_merge", "consolidate identical cells") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" opt_share [options] [selection]\n");
log(" opt_merge [options] [selection]\n");
log("\n");
log("This pass identifies cells with identical type and input signals. Such cells\n");
log("are then merged to one cell.\n");
@ -328,7 +328,7 @@ struct OptSharePass : public Pass {
int total_count = 0;
for (auto module : design->selected_modules()) {
OptShareWorker worker(design, module, mode_nomux, mode_share_all);
OptMergeWorker worker(design, module, mode_nomux, mode_share_all);
total_count += worker.total_count;
}
@ -336,6 +336,6 @@ struct OptSharePass : public Pass {
design->scratchpad_set_bool("opt.did_something", true);
log("Removed a total of %d cells.\n", total_count);
}
} OptSharePass;
} OptMergePass;
PRIVATE_NAMESPACE_END