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Author SHA1 Message Date
whitequark
44a9dcbbbf
Merge pull request #1242 from jfng/fix-proc_prune-partial 
proc_prune: Promote partially redundant assignments.
 2019-08-03 07:08:41 +00:00
Miodrag Milanovic
2b4e50ac3d Visual Studio build fix 2019-08-02 17:08:59 +02:00
Clifford Wolf
0917a5cf72
Merge pull request #1238 from mmicko/vsbuild_fix 
Visual Studio build fix
 2019-08-02 17:07:39 +02:00
Miodrag Milanovic
2ec5a3ec92 Fix linking issue for new mxe and pthread 2019-08-02 16:55:14 +02:00
Miodrag Milanovic
ce0de937f4 Fix yosys linking for mxe 2019-08-02 16:55:14 +02:00
Miodrag Milanovic
bf59f31b43 New mxe hacks needed to support 2ca237e 2019-08-02 16:55:14 +02:00
Miodrag Milanovic
e9c5f1b346 Fix formatting for msys2 mingw build using GetSize 2019-08-02 16:55:14 +02:00
Clifford Wolf
f4ae6afc22
Merge pull request #1239 from mmicko/mingw_fix 
Fix formatting for msys2 mingw build
 2019-08-02 16:37:57 +02:00
Eddie Hung
c39b1a6fcf Add comment about supporting $dffe in ice40_dsp 2019-08-01 15:13:18 -07:00
Eddie Hung
ed7540a46f Pack P register properly 2019-08-01 15:10:43 -07:00
Eddie Hung
105aaeaf59 Trim Y_WIDTH 2019-08-01 14:33:16 -07:00
Eddie Hung
65de9aaaa9 Add DSP_SIGNEDONLY back 2019-08-01 14:29:00 -07:00
Eddie Hung
915f4e34bf DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH 2019-08-01 13:20:34 -07:00
Eddie Hung
fc0b5d5ab6 Change $__softmul back to $mul 2019-08-01 12:45:14 -07:00
Eddie Hung
e19d33b003 Cope with sign extension in mul2dsp 2019-08-01 12:44:56 -07:00
Eddie Hung
332b86491d Revert "Do not do sign extension in techmap; let packer do it" 
This reverts commit 595a8f032f.
 2019-08-01 12:17:14 -07:00
Eddie Hung
ed303b07b7 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-01 12:02:16 -07:00
Eddie Hung
7e86c8bcfb Fix B_WIDTH > DSP_B_MAXWIDTH case 2019-08-01 10:01:43 -07:00
Eddie Hung
c54a39069d CO is sign extension only if signed multiplier 2019-08-01 10:00:49 -07:00
Eddie Hung
e3c39cc450 Fix typo 2019-08-01 10:00:01 -07:00
Eddie Hung
e8a2d10982
Merge pull request #1236 from YosysHQ/eddie/xc6s_brams_map 
xc6s_brams_map.v: RST -> RSTBRST for RAMB8BWER
 2019-08-01 09:38:55 -07:00
Miodrag Milanovic
7a65ed19a5 Fix linking issue for new mxe and pthread 2019-08-01 17:30:02 +02:00
Miodrag Milanovic
3f633690ae Fix yosys linking for mxe 2019-08-01 17:28:07 +02:00
Miodrag Milanovic
f767179c75 New mxe hacks needed to support 2ca237e 2019-08-01 17:28:07 +02:00
Miodrag Milanovic
28b7053a01 Fix formatting for msys2 mingw build using GetSize 2019-08-01 17:27:34 +02:00
Jean-François Nguyen
320bf2fde5 proc_prune: Promote partially redundant assignments. 2019-08-01 13:09:55 +02:00
Clifford Wolf
292f03355a Update JSON front-end to process new attr/param encoding 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-01 12:48:22 +02:00
Clifford Wolf
15fae357f6 Implement improved JSON attr/param encoding 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-01 12:34:52 +02:00
Eddie Hung
d2c33863d0 Do not compute sign bit if result is zero 2019-07-31 16:04:19 -07:00
Eddie Hung
60c4887d15 For signed multipliers, compute sign bit separately... 2019-07-31 15:45:41 -07:00
Eddie Hung
e4a638c292 Restore old CO behaviour 2019-07-31 15:45:15 -07:00
Eddie Hung
84c7a562e5 Helper: SigSpec::operator[] to accept negative indices 2019-07-31 12:18:03 -07:00
Jim Lawson
3b8c917025 Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences. 
Use FIRRTL spec vlaues for definition of FIRRTL widths.
Added support for '$pos`, `$pow` and `$xnor` cells.
Enable tests/simple/operators.v since all operators tested there are now supported.
Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
 2019-07-31 09:27:38 -07:00
Clifford Wolf
acd8bc0a74
Merge pull request #1233 from YosysHQ/clifford/defer 
Call "read_verilog" with -defer from "read"
 2019-07-31 13:30:52 +02:00
Miodrag Milanovic
35d28de478 Visual Studio build fix 2019-07-31 09:10:24 +02:00
Jim Lawson
e8341d949f Merge remote-tracking branch 'upstream/master' 2019-07-30 16:04:27 -07:00
Eddie Hung
66806085db RST -> RSTBRST for RAMB8BWER 2019-07-29 16:05:44 -07:00
Eddie Hung
b4f38cca77
Merge pull request #1228 from YosysHQ/dave/yy_buf_size 
verilog_lexer: Increase YY_BUF_SIZE to 65536
 2019-07-29 09:16:09 -07:00
David Shah
ccf759864a
Merge pull request #1234 from mmicko/fix_gzip_no_exist 
Fix case when file does not exist
 2019-07-29 15:50:20 +01:00
Miodrag Milanovic
3e4307c104 Fix case when file does not exist 2019-07-29 12:29:13 +02:00
Clifford Wolf
5be5bd0fb6 Update README to use "read" instead of "read_verilog" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-29 10:40:30 +02:00
Clifford Wolf
fc462c8243 Call "read_verilog" with -defer from "read" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-29 10:29:36 +02:00
Bogdan Vukobratovic
c075486c59 Reimplement opt_share to work on $alu and $pmux 2019-07-28 16:03:54 +02:00
David Shah
6538671c84
Merge pull request #1226 from YosysHQ/dave/gzip 
Add support for gzip'd input files
 2019-07-27 07:40:38 +01:00
Eddie Hung
2f71c2c219 Fix spacing 2019-07-26 15:30:51 -07:00
Eddie Hung
07e38d8d5c Update test_autotb doc to reflect default value of zero 2019-07-26 12:37:30 -07:00
Eddie Hung
8cecad5059 Add doc for "test_autotb -seed" option 2019-07-26 12:26:54 -07:00
Eddie Hung
4c25d1a76f Pop the CO bit from O 2019-07-26 10:27:30 -07:00
Eddie Hung
c1a05f4557 Allow adders/accumulators with 33 bits using CO output 2019-07-26 10:15:36 -07:00
David Shah
82a2972068 Update CHANGELOG 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-26 16:45:51 +01:00