mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 01:25:33 +00:00
Code Activity
6876 commits 95 branches 53 tags 45 MiB
Commit graph

6876 commits

This branch
This branch
All branches
Author SHA1 Message Date
Eddie Hung
1d88887cfd Add a unique argument to pmgen's nusers() 2019-08-23 14:32:17 -07:00
Eddie Hung
8ecfd55d5a Update doc 2019-08-23 14:16:41 -07:00
Eddie Hung
3d7f4aa0c8 Remove (* init *) entry when consumed into SRL 2019-08-23 13:56:01 -07:00
Eddie Hung
967a36c125 indo -> into 2019-08-23 13:16:50 -07:00
Eddie Hung
a1f78eab04 indo -> into 2019-08-23 13:15:41 -07:00
Eddie Hung
5939ffdc07 Forgot to slice 2019-08-23 13:06:59 -07:00
Eddie Hung
242b3083ea Cope with possibility that D could connect to Q on same cell 2019-08-23 13:06:31 -07:00
Eddie Hung
4a4e28b55e Revert earliest to gcc-4.8, compile iverilog with default compiler 2019-08-23 12:29:57 -07:00
Eddie Hung
b3dc28cf65 Revert "Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!" 
This reverts commit c82b2fa31f.
 2019-08-23 12:29:57 -07:00
Eddie Hung
fcb102d60e Remove .0 from clang-8.0 2019-08-23 12:29:57 -07:00
Eddie Hung
fdc438e551 Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?! 2019-08-23 12:29:57 -07:00
Eddie Hung
bf40f2f895 bionic -> xenial as its on whitelist 2019-08-23 12:29:57 -07:00
Eddie Hung
43927e5910 Bump gcc from 4.8 to 4.9 as undefined reference 
... to `__warn_memset_zero_len'.
Also remove gcc-6, bump gcc-7 to gcc-9, clang from 5.0 to 8.0
 2019-08-23 12:29:50 -07:00
Eddie Hung
cee30deef5 Mention shregmap -tech xilinx is superseded 2019-08-23 12:24:25 -07:00
Eddie Hung
08139aa53a xilinx_srl now copes with word-level flops $dff{,e} 2019-08-23 12:22:46 -07:00
Eddie Hung
18b64609c2 xilinx_srl to use 'slice' features of pmgen for word level 2019-08-23 12:22:06 -07:00
Eddie Hung
f4fd41d5d2 Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl 2019-08-23 11:35:06 -07:00
Eddie Hung
78b7d8f531 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-23 11:32:44 -07:00
Eddie Hung
20f4d191b5 Merge branch 'master' into mwk/xilinx_bufgmap 2019-08-23 11:24:19 -07:00
Eddie Hung
509c353fe9 Forgot one 2019-08-23 11:23:50 -07:00
Eddie Hung
0d0ad15898 Merge branch 'master' into mwk/xilinx_bufgmap 2019-08-23 11:23:31 -07:00
Eddie Hung
a270af00cc Put abc_* attributes above port 2019-08-23 11:21:44 -07:00
Eddie Hung
a0d85393e3 Check clkbuf_inhibit=1 is ignored for custom selection 2019-08-23 11:15:26 -07:00
Eddie Hung
619f2414e5 clkbufmap to only check clkbuf_inhibit if no selection given 2019-08-23 11:14:42 -07:00
Eddie Hung
5628e2ec53 Add simple clkbufmap tests 2019-08-23 11:10:02 -07:00
Eddie Hung
d62c10d641 tests/techmap/run-test.sh to cope with *.ys 2019-08-23 11:09:50 -07:00
Eddie Hung
4c0404ae02 Mention clkbuf_inhibit can be overridden 2019-08-23 10:24:59 -07:00
Eddie Hung
4d89c3f468 Review comment from @cliffordwolf 2019-08-23 10:03:41 -07:00
Eddie Hung
6872805a3e Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap 2019-08-23 10:00:50 -07:00
Miodrag Milanovic
55aa444e05 Make macOS depenency clear 2019-08-23 09:15:50 -07:00
Eddie Hung
bb2d5bc4f8
Merge pull request #1326 from mmicko/doc-update 
Make macOS dependency clear
 2019-08-23 09:12:58 -07:00
Eddie Hung
10c41a5cf5 Blocking assignment 2019-08-23 09:11:04 -07:00
SergeyDegtyar
c29380b381 Fix pull request 2019-08-23 18:55:01 +03:00
Clifford Wolf
55bf8f69e0 Fix port hanlding in pmgen 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-23 16:26:54 +02:00
Clifford Wolf
adb81ba386 Add pmgen slices and choices 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-23 16:15:50 +02:00
SergeyDegtyar
3c10f58d04 Fix run-test.sh; Add new test for dpram. 2019-08-23 17:00:16 +03:00
SergeyDegtyar
0b25dbf1c6 Fix path in run-test.sh 2019-08-23 12:40:14 +03:00
Miodrag Milanovic
c618ae43b9 Make macOS depenency clear 2019-08-23 10:37:50 +02:00
Sergey
27134be135
Merge pull request #1 from YosysHQ/Sergey/tests_ice40 
tests_ice40 improvements
 2019-08-23 06:50:19 +03:00
Eddie Hung
fe1b2337fd Do not propagate mem2reg attribute through to result 2019-08-22 16:57:59 -07:00
Eddie Hung
36cf0a3dd5 Remove adffs_tb.v 2019-08-22 16:50:14 -07:00
Eddie Hung
51ffb093b5 In sat: 'x' in init attr should not override constant 2019-08-22 16:43:08 -07:00
Eddie Hung
2b37a093e9 In sat: 'x' in init attr should not override constant 2019-08-22 16:42:19 -07:00
Eddie Hung
66607845ec Remove Xilinx test 2019-08-22 16:18:07 -07:00
Eddie Hung
53fed4f7e9 Actually, there might not be any harm in updating sigmap... 2019-08-22 16:16:56 -07:00
Eddie Hung
cfafd360d5 Add comment as per @cliffordwolf 2019-08-22 16:16:56 -07:00
Eddie Hung
e7a8cdbccf Add shregmap -tech xilinx test 2019-08-22 16:16:54 -07:00
Eddie Hung
8691596d19 Revert "Try way that doesn't involve creating a new wire" 
This reverts commit 2f427acc9e.
 2019-08-22 16:16:34 -07:00
Eddie Hung
5ff75b1cdc Try way that doesn't involve creating a new wire 2019-08-22 16:16:34 -07:00
Eddie Hung
e1fff34dde If d_bit already in sigbit_chain_next, create extra wire 2019-08-22 16:16:34 -07:00