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Author SHA1 Message Date
Eddie Hung
54f3237720 Fix gcc warning of potentially uninitialised 2019-06-20 22:10:43 -07:00
Eddie Hung
8e56cfb6bb write_xaiger to flatten 1'bx/1'bz to 1'b0 again 2019-06-20 19:41:27 -07:00
Eddie Hung
0e97e6a00d Fix simple_abc9/generate test with 1'bx at MSB 2019-06-20 19:41:27 -07:00
Eddie Hung
ad36eb24c0 Fix different abc9 test 2019-06-20 19:41:27 -07:00
Eddie Hung
9faeba7a66 Fix broken abc9.v test due to inout being 1'bx 2019-06-20 19:41:27 -07:00
Eddie Hung
eb09ea6d54 Run simple_abc9 tests 2019-06-20 19:41:27 -07:00
Eddie Hung
e612dade12 Merge remote-tracking branch 'origin/master' into xaig 2019-06-20 19:00:36 -07:00
Eddie Hung
014606affe Fix issue with part of PI being 1'bx 2019-06-20 17:38:16 -07:00
Eddie Hung
f11c9a419b Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc 2019-06-20 17:38:16 -07:00
Eddie Hung
4e5836a5fb Handle COs driven by 1'bx 2019-06-20 17:38:04 -07:00
Eddie Hung
3f34779d64 Do not call "setundef -zero" in abc9 2019-06-20 17:38:04 -07:00
Eddie Hung
f2d541962e write_xaiger to skip POs driven by 1'bx 2019-06-20 17:37:54 -07:00
Clifford Wolf
477e566e8d Fix typo, fixes #1095 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 15:34:52 +02:00
Clifford Wolf
06eb87bcb7 Improve shregmap help message, fixes #1113 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 15:23:55 +02:00
Clifford Wolf
a8c85d1b4b Update some .gitignore files 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 14:27:57 +02:00
Clifford Wolf
11ec7b2aec Fix typo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 12:23:07 +02:00
Clifford Wolf
7f1461d64b Merge branch 'towoe-unpacked_arrays' 2019-06-20 12:06:58 +02:00
Clifford Wolf
6a6dd5e057 Add proper test for SV-style arrays 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 12:06:07 +02:00
Clifford Wolf
2428fb7dc2 Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towoe-unpacked_arrays 2019-06-20 12:03:00 +02:00
Eddie Hung
3b1e5264d8
Merge pull request #1111 from acw1251/help_summary_fixes 
Fixed the help summary line for a few commands
 2019-06-19 15:30:50 -07:00
acw1251
ce29ede801 Fixed small typo in ice40_unlut help summary 2019-06-19 16:39:46 -04:00
acw1251
0d888ee7ed Fixed the help summary line for a few commands 2019-06-19 15:27:04 -04:00
Eddie Hung
96ade54993 Fix bug in #1078, add entry to CHANGELOG 2019-06-19 09:51:11 -07:00
Clifford Wolf
8395f837c3
Merge pull request #1109 from YosysHQ/clifford/fix1106 
Add "read_verilog -pwires" feature
 2019-06-19 17:25:39 +02:00
Clifford Wolf
ec4565009a Add "read_verilog -pwires" feature, closes #1106 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 14:38:50 +02:00
Clifford Wolf
5a1f1caa44
Merge pull request #1105 from YosysHQ/clifford/fixlogicinit 
Improve handling of initial/default values
 2019-06-19 13:53:07 +02:00
Tobias Wölfel
8b8af10f5e Unpacked array declaration using size 
Allows fixed-sized array dimension specified by a single number.

This commit is based on the work from PeterCrozier
https://github.com/YosysHQ/yosys/pull/560.
But is split out of the original work.
 2019-06-19 12:47:48 +02:00
Clifford Wolf
c330379870 Make tests/aiger less chatty 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 12:20:35 +02:00
Clifford Wolf
fa5fc3f6af Add defvalue test, minor autotest fixes for .sv files 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 12:12:08 +02:00
Clifford Wolf
3da5288ce0 Use input default values in hierarchy pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 11:49:20 +02:00
Clifford Wolf
8d0cd529c9 Add defaultvalue attribute 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 11:37:11 +02:00
Clifford Wolf
6d64e242ba Fix handling of "logic" variables with initial value 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 11:25:11 +02:00
Clifford Wolf
b3441935b1
Merge pull request #1100 from bwidawsk/home 
Support ~ in filename parsing
 2019-06-19 10:52:59 +02:00
Clifford Wolf
eb3b9fb24a
Merge pull request #1104 from whitequark/case-semantics 
Clarify switch/case semantics in RTLIL
 2019-06-19 10:50:32 +02:00
whitequark
addf01d45d Explain exact semantics of switch and case rules in the manual. 2019-06-19 05:22:40 +00:00
whitequark
df6576edc8 In RTLIL::Module::check(), check process invariants. 2019-06-19 05:22:13 +00:00
Ben Widawsky
4a18e19fb8 Support filename rewrite in backends 
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-06-18 14:39:52 -07:00
Ben Widawsky
468c41d997 Support ~ for home directory 
This is tested on Linux only

v2:
Wrap functioanlity in ifndef _WIN32 (eddiehung)
Find '~/' instead of '~' (cliffordwolf)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-06-18 14:38:40 -07:00
Eddie Hung
8e0a47fb92 Really permute Xilinx LUT mappings as default LUT6.I5:A6 2019-06-18 11:48:48 -07:00
Eddie Hung
8f5e6d73ff Revert "Fix (do not) permute LUT inputs, but permute mux selects" 
This reverts commit da3d2eedd2.
 2019-06-18 11:35:21 -07:00
Eddie Hung
b304744d15 Clean up 2019-06-18 09:50:37 -07:00
Eddie Hung
da3d2eedd2 Fix (do not) permute LUT inputs, but permute mux selects 2019-06-18 09:49:57 -07:00
Clifford Wolf
64947453e2
Merge pull request #1086 from udif/pr_elab_sys_tasks2 
Fixed broken $error()/$info/$warning() on non-generate blocks (within always/initial blocks)
 2019-06-18 16:52:08 +02:00
Eddie Hung
608a95eb01 Fix copy-pasta issue 2019-06-17 22:29:22 -07:00
Eddie Hung
2a35c4ef94 Permute INIT for +/xilinx/lut_map.v 2019-06-17 22:24:35 -07:00
Eddie Hung
75f8b4cf10 Simplify comment 2019-06-17 19:14:41 -07:00
Eddie Hung
840562943f Update LUT7/8 delays to take account for [ABC]OUTMUX delay 2019-06-17 17:06:01 -07:00
Eddie Hung
4d6d593fe3 &scorr before &sweep, remove &retime as recommended 2019-06-17 13:32:08 -07:00
Eddie Hung
63fc879a5f Copy not move parameters/attributes 2019-06-17 13:19:45 -07:00
Eddie Hung
b45d06d7a3 Fix leak removing cells during ABC integration; also preserve attr 2019-06-17 12:54:24 -07:00