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	Merge pull request #1111 from acw1251/help_summary_fixes
Fixed the help summary line for a few commands
This commit is contained in:
		
						commit
						3b1e5264d8
					
				
					 4 changed files with 6 additions and 6 deletions
				
			
		|  | @ -23,7 +23,7 @@ USING_YOSYS_NAMESPACE | |||
| PRIVATE_NAMESPACE_BEGIN | ||||
| 
 | ||||
| struct BlackboxPass : public Pass { | ||||
| 	BlackboxPass() : Pass("blackbox", "change type of cells in the design") { } | ||||
| 	BlackboxPass() : Pass("blackbox", "convert modules into blackbox modules") { } | ||||
| 	void help() YS_OVERRIDE | ||||
| 	{ | ||||
| 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 | ||||
|  |  | |||
|  | @ -180,7 +180,7 @@ struct AssertpmuxWorker | |||
| }; | ||||
| 
 | ||||
| struct AssertpmuxPass : public Pass { | ||||
| 	AssertpmuxPass() : Pass("assertpmux", "convert internal signals to module ports") { } | ||||
| 	AssertpmuxPass() : Pass("assertpmux", "adds asserts for parallel muxes") { } | ||||
| 	void help() YS_OVERRIDE | ||||
| 	{ | ||||
| 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 | ||||
|  | @ -195,8 +195,8 @@ struct AssertpmuxPass : public Pass { | |||
| 		log("\n"); | ||||
| 		log("    -always\n"); | ||||
| 		log("        usually the $pmux condition is only checked when the $pmux output\n"); | ||||
| 		log("        is used be the mux tree it drives. this option will deactivate this\n"); | ||||
| 		log("        additional constrained and check the $pmux condition always.\n"); | ||||
| 		log("        is used by the mux tree it drives. this option will deactivate this\n"); | ||||
| 		log("        additional constraint and check the $pmux condition always.\n"); | ||||
| 		log("\n"); | ||||
| 	} | ||||
| 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE | ||||
|  |  | |||
|  | @ -24,7 +24,7 @@ USING_YOSYS_NAMESPACE | |||
| PRIVATE_NAMESPACE_BEGIN | ||||
| 
 | ||||
| struct CutpointPass : public Pass { | ||||
| 	CutpointPass() : Pass("cutpoint", "add hi/lo cover cells for each wire bit") { } | ||||
| 	CutpointPass() : Pass("cutpoint", "adds formal cut points to the design") { } | ||||
| 	void help() YS_OVERRIDE | ||||
| 	{ | ||||
| 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 | ||||
|  |  | |||
|  | @ -74,7 +74,7 @@ static void run_ice40_unlut(Module *module) | |||
| } | ||||
| 
 | ||||
| struct Ice40UnlutPass : public Pass { | ||||
| 	Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: perform simple optimizations") { } | ||||
| 	Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: transform SB_LUT4 cells to $lut cells") { } | ||||
| 	void help() YS_OVERRIDE | ||||
| 	{ | ||||
| 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 | ||||
|  |  | |||
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