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10114 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Eddie Hung
af36943cb9 Preserve size of $genval$-s in for loops 2019-12-11 16:52:37 -08:00
Eddie Hung
151f7533e8 Add testcase 2019-12-11 16:52:37 -08:00
Eddie Hung
2666482282 Update README.md :: abc_ -> abc9_ 2019-12-11 16:38:43 -08:00
Eddie Hung
f022645cd2 Fix bitwidth mismatch; suppresses iverilog warning 2019-12-11 13:02:07 -08:00
Eddie Hung
9a892199f7 Suppress warning message for init[i] = 1'bx 2019-12-11 11:27:10 -08:00
Eddie Hung
e75ca29b19 Add test: 'Warning: ignoring initial value on non-register: \o' 2019-12-11 11:26:54 -08:00
Gustavo Romero
993a77d19b manual: Fix text in Abstract section 2019-12-11 08:22:08 -03:00
David Shah
613334d9dc
Merge pull request #1564 from ZirconiumX/intel_housekeeping 
Intel housekeeping
 2019-12-11 08:46:10 +00:00
Dan Ravensloft
85a14895ca synth_intel: a10gx -> arria10gx 2019-12-10 13:48:10 +00:00
Dan Ravensloft
eab3272cde synth_intel: cyclone10 -> cyclone10lp 2019-12-10 13:47:58 +00:00
Eddie Hung
7e5602ad17
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr 
Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
 2019-12-09 17:38:48 -08:00
Eddie Hung
49c2e59b2a Fix comment 2019-12-09 15:44:19 -08:00
Eddie Hung
fb203d2a2c ice40_opt to restore attributes/name when unwrapping 2019-12-09 14:29:29 -08:00
Eddie Hung
36a88be609 ice40_wrapcarry -unwrap to preserve 'src' attribute 2019-12-09 14:28:54 -08:00
Eddie Hung
eff858cd33 unmap $__ICE40_CARRY_WRAPPER in test 2019-12-09 14:20:35 -08:00
Eddie Hung
bbdf2452b3 -unwrap to create $lut not SB_LUT4 for opt_lut 2019-12-09 13:27:09 -08:00
Eddie Hung
705e520a52 Add a quick testcase for unknown modules as inout 2019-12-09 13:14:46 -08:00
Eddie Hung
500ed9b501 Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4 2019-12-09 12:45:22 -08:00
Eddie Hung
e05372778a ice40_wrapcarry to really preserve attributes via -unwrap option 2019-12-09 11:48:28 -08:00
David Shah
184c0e796a ecp5: Add support for mapping PRLD FFs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-07 13:04:36 +00:00
Miodrag Milanovic
49c9b63e0f Fix for non-deterministic test 2019-12-07 11:09:25 +01:00
Eddie Hung
a46a7e8a67 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-06 23:22:52 -08:00
Eddie Hung
ecb0c68f07
Merge pull request #1555 from antmicro/fix-macc-xilinx-test 
tests: arch: xilinx: Change order of arguments in macc.sh
 2019-12-06 23:04:04 -08:00
Eddie Hung
946d5854c0 Drop keep=0 attributes on SB_CARRY 2019-12-06 17:27:47 -08:00
Eddie Hung
91467938c4 Stray newline 2019-12-06 17:08:19 -08:00
Eddie Hung
f2ac36de4a write_xaiger to inst each cell type once, do not call techmap/aigmap 2019-12-06 17:06:10 -08:00
Eddie Hung
98c9ea605b techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger 2019-12-06 17:05:02 -08:00
Eddie Hung
ab667d3d47 Call abc9 with "&write -n", and parse_xaiger() to cope 2019-12-06 16:35:57 -08:00
Eddie Hung
c767525441 Remove creation of $abc9_control_wire 2019-12-06 16:23:09 -08:00
Eddie Hung
69d8c1386a Do not connect undriven POs to 1'bx 2019-12-06 16:21:06 -08:00
Eddie Hung
fce527f4f7 Fix abc9 re-integration, remove abc9_control_wire, use cell->type as 
as part of clock domain for mergeability class
 2019-12-06 16:20:18 -08:00
Eddie Hung
1f96de04c9 Fix writing non-whole modules, including inouts and keeps 2019-12-06 16:19:10 -08:00
Jan Kowalewski
dcb30b5f4a tests: arch: xilinx: Change order of arguments in macc.sh 2019-12-06 09:15:49 +01:00
Eddie Hung
ec0acc9f85 abc9 to use mergeability class to differentiate sync/async 2019-12-06 00:12:37 -08:00
Eddie Hung
a682a3cf93 write_xaiger to support part-selected modules again 2019-12-05 17:54:43 -08:00
Eddie Hung
01a3cc29ba abc9 to do clock partitioning again 2019-12-05 17:26:22 -08:00
Eddie Hung
02786b0aa0 Remove clkpart 2019-12-05 17:25:26 -08:00
Eddie Hung
864bff14f1 Revert "Special abc9_clock wire to contain only clock signal" 
This reverts commit 6a2eb5d8f9.
 2019-12-05 11:11:53 -08:00
Clifford Wolf
7dece7955e
Merge pull request #1551 from whitequark/manual-cell-operands 
Clarify semantics of comb cells, in particular shifts
 2019-12-05 08:24:24 -08:00
Eddie Hung
a7e0cca480 Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPER 2019-12-05 07:01:18 -08:00
Eddie Hung
d8fbf88980 Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER 2019-12-05 07:01:02 -08:00
whitequark
72a5674c03 manual: document $dffe, $dffsr, $_DFFE_*, $_DFFSR_* cells. 2019-12-05 10:28:43 +00:00
Eddie Hung
0d248dd7ba Missing wire declaration 2019-12-04 23:04:40 -08:00
Eddie Hung
19bc429482 abc9_map.v to transform INIT=1 to INIT=0 2019-12-04 21:36:41 -08:00
Eddie Hung
258a34e6f1 Oh deary me 2019-12-04 20:33:24 -08:00
Eddie Hung
c8a7bc5d3a Bump ABC to get "&verify -s" fix 2019-12-04 16:37:56 -08:00
Eddie Hung
b43986c5a1 output reg Q -> output Q to suppress warning 2019-12-04 16:34:34 -08:00
Eddie Hung
31ef4cc704 abc9_map.v to do `zinit' and make INIT = 1'b0 2019-12-04 16:11:02 -08:00
whitequark
e97e33d00d kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr. 
Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.

Also fix the Verilog frontend to never emit such constructs.
 2019-12-04 11:59:36 +00:00
whitequark
ec4c9267b3 manual: document behavior of many comb cells more precisely. 2019-12-04 11:32:14 +00:00