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Author SHA1 Message Date
Clifford Wolf
65f197e28f Add check for valid macro names in macro definitions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-07 13:30:03 +01:00
Pepijn de Vos
0e5dbc4abc fix wide luts 2019-11-06 19:48:18 +01:00
Marcin Kościelnicki
c4bd318e76 synth_xilinx: Merge blackbox primitive libraries. 
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.

Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included.  Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.

Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).

Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
 2019-11-06 15:11:27 +01:00
Clifford Wolf
5110a34dd7 Fix write_aiger bug added in 524af21 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-04 14:25:13 +01:00
Clifford Wolf
c3ad375200 Add CodingReadme section on script passes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-31 10:46:20 +01:00
Pepijn de Vos
df8390f5df don't cound exact luts in big muxes; futile and fragile 2019-10-30 14:58:25 +01:00
Pepijn de Vos
0f6269b04c add IOBUF 2019-10-28 15:33:05 +01:00
Pepijn de Vos
903f997391 add tristate buffer and test 2019-10-28 15:18:01 +01:00
Pepijn de Vos
9517525224 do not use wide luts in testcase 2019-10-28 14:40:12 +01:00
Pepijn de Vos
4ec4d5ec7e actually run the gowin tests 2019-10-28 14:28:03 +01:00
Pepijn de Vos
2f5e9e9885 More formatting 2019-10-28 13:10:12 +01:00
Pepijn de Vos
c1921b4561 really really fix formatting maybe 2019-10-28 13:01:20 +01:00
Pepijn de Vos
293b2c2de5 undo formatting fuckup 2019-10-28 12:57:12 +01:00
Pepijn de Vos
f88335a8a5 add wide luts 2019-10-28 12:49:08 +01:00
Pepijn de Vos
5fad53b504 add 32-bit BRAM and byte-enables 2019-10-28 10:33:27 +01:00
Clifford Wolf
81876a3734
Merge pull request #1393 from whitequark/write_verilog-avoid-init 
write_verilog: do not print (*init*) attributes on regs
 2019-10-27 10:25:01 +01:00
Pepijn de Vos
8226f2db0b ALU sim tweaks 2019-10-24 13:39:43 +02:00
Clifford Wolf
84982b3083 Improve naming scheme for (VHDL) modules imported from Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-24 12:13:50 +02:00
David Shah
34dadd9ab2
Merge pull request #1455 from YosysHQ/dave/ultrascaleplus 
Add BRAM and URAM mapping for UltraScale[+]
 2019-10-24 08:14:20 +01:00
Clifford Wolf
d49c6b2cba Add "verific -L" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-24 09:14:03 +02:00
David Shah
e135ed5d80 ice40: Add post-pnr ICESTORM_RAM model and fix FFs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-23 18:44:34 +01:00
David Shah
37dd3ad3fe ice40: Support for post-pnr timing simulation 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-23 12:03:31 +01:00
David Shah
3506eaf290 xilinx: Add URAM288 mapping for xcup 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-23 11:47:44 +01:00
David Shah
6769d31ddb xilinx: Add support for UltraScale[+] BRAM mapping 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-23 11:47:37 +01:00
Clifford Wolf
f02623abb5 Bugfix in smtio vcd handling of $-identifiers 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-23 00:04:34 +02:00
Marcin Kościelnicki
7b350cacd4 xilinx: Support multiplier mapping for all families. 
This supports several older families that are not yet supported for
actual logic synthesis — the intention is to add them soon.
 2019-10-22 18:06:57 +02:00
Clifford Wolf
a3a7bb9bf7
Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg 
Call memory_dff before DSP mapping to reserve registers (fixes #1447)
 2019-10-22 17:36:54 +02:00
Pepijn de Vos
83fbfe0964 Add some tests 
Copied from Efinix.

* fsm is broken
* latch and tribuf are not implemented yet
* memory maps to dram
 2019-10-21 16:25:15 +02:00
Pepijn de Vos
03457ee13e add a few more missing dff 2019-10-21 16:08:13 +02:00
Clifford Wolf
5025aab8c9 Add "verilog_defines -list" and "verilog_defines -reset" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-21 13:35:56 +02:00
Clifford Wolf
4033ff8c2e Fix handling of "restrict" in Verific front-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-21 12:39:28 +02:00
Pepijn de Vos
8a2699c40c add negedge DFF 2019-10-21 12:31:11 +02:00
Pepijn de Vos
af7bdd598e use ADDSUB ALU mode to remove inverters 2019-10-21 12:00:27 +02:00
Pepijn de Vos
69fb3b8db2 Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin 2019-10-21 10:51:34 +02:00
David Shah
fa989e59e5 ecp5: Pass -nomfs to abc9 
Fixes #1459

Signed-off-by: David Shah <dave@ds0.me>
 2019-10-20 10:30:41 +01:00
Miodrag Milanović
f2aa2d1bb4
Merge pull request #1457 from xobs/python-binary-name 
Makefile: don't assume python is called `python3`
 2019-10-19 08:58:02 +02:00
Sean Cross
82f60ba938 Makefile: don't assume python is called python3 
On some architectures, notably on Windows, the official name for the
Python binary from python.org is `python`.  The build system assumes
that python is called `python3`, which breaks under this architecture.

There is already infrastructure in place to determine the name of the
Python binary when building PYOSYS.  Since Python is now always required
to build Yosys, enable this check universally which sets the
`PYTHON_EXECUTABLE` variable.

Then, reuse this variable in other Makefiles as necessary, rather than
hardcoding `python3` everywhere.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-10-19 14:04:52 +08:00
Miodrag Milanović
e8ef3fcdfc
Merge pull request #1454 from YosysHQ/mmicko/common_tests 
Share common tests
 2019-10-18 14:29:44 +02:00
Miodrag Milanovic
190b40341a fixed error 2019-10-18 13:15:36 +02:00
Miodrag Milanovic
9bd9db56c8 Unify verilog style 2019-10-18 12:50:24 +02:00
Miodrag Milanovic
12383f37b2 Common memory test now shared 2019-10-18 12:33:35 +02:00
Miodrag Milanovic
477702b8c9 Remove not needed tests 2019-10-18 12:20:35 +02:00
Miodrag Milanovic
5603595e5c Share common tests 2019-10-18 12:19:59 +02:00
Miodrag Milanovic
ab98f2dccf fix yosys path 2019-10-18 11:18:53 +02:00
Miodrag Milanovic
56f9482675 Fix path to yosys 2019-10-18 11:12:03 +02:00
Miodrag Milanovic
c2ec7ca703 Moved all tests in arch sub directory 2019-10-18 11:06:12 +02:00
Miodrag Milanovic
3c41599ee1 Add async2sync 2019-10-18 11:00:27 +02:00
Miodrag Milanović
0568920d79
Merge pull request #1435 from YosysHQ/mmicko/efinix 
Add tests for Efinix architecture (contd)
 2019-10-18 10:54:35 +02:00
Miodrag Milanović
b4d7650548
Merge branch 'master' into mmicko/efinix 2019-10-18 10:54:28 +02:00
Miodrag Milanović
ab4899a2d0
Merge pull request #1434 from YosysHQ/mmicko/anlogic 
Add tests for Anlogic architecture (contd)
 2019-10-18 10:54:04 +02:00