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Merge pull request #1454 from YosysHQ/mmicko/common_tests

Share common tests
This commit is contained in:
Miodrag Milanović 2019-10-18 14:29:44 +02:00 committed by GitHub
commit e8ef3fcdfc
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GPG key ID: 4AEE18F83AFDEB23
166 changed files with 455 additions and 1763 deletions

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@ -713,12 +713,12 @@ test: $(TARGETS) $(EXTRA_TARGETS)
+cd tests/opt && bash run-test.sh
+cd tests/aiger && bash run-test.sh $(ABCOPT)
+cd tests/arch && bash run-test.sh
+cd tests/ice40 && bash run-test.sh $(SEEDOPT)
+cd tests/arch/ice40 && bash run-test.sh $(SEEDOPT)
+cd tests/arch/xilinx && bash run-test.sh $(SEEDOPT)
+cd tests/arch/ecp5 && bash run-test.sh $(SEEDOPT)
+cd tests/arch/efinix && bash run-test.sh $(SEEDOPT)
+cd tests/arch/anlogic && bash run-test.sh $(SEEDOPT)
+cd tests/rpc && bash run-test.sh
+cd tests/efinix && bash run-test.sh $(SEEDOPT)
+cd tests/anlogic && bash run-test.sh $(SEEDOPT)
+cd tests/ecp5 && bash run-test.sh $(SEEDOPT)
+cd tests/xilinx && bash run-test.sh $(SEEDOPT)
@echo ""
@echo " Passed \"make test\"."
@echo ""

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@ -1,13 +0,0 @@
module top
(
input [3:0] x,
input [3:0] y,
output [3:0] A,
output [3:0] B
);
assign A = x + y;
assign B = x - y;
endmodule

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@ -1,17 +0,0 @@
module top (
out,
clk,
reset
);
output [7:0] out;
input clk, reset;
reg [7:0] out;
always @(posedge clk, posedge reset)
if (reset) begin
out <= 8'b0 ;
end else
out <= out + 1;
endmodule

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@ -1,15 +0,0 @@
module dff
( input d, clk, output reg q );
always @( posedge clk )
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule

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@ -1,55 +0,0 @@
module fsm (
clock,
reset,
req_0,
req_1,
gnt_0,
gnt_1
);
input clock,reset,req_0,req_1;
output gnt_0,gnt_1;
wire clock,reset,req_0,req_1;
reg gnt_0,gnt_1;
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end else
case(state)
IDLE : if (req_0 == 1'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1 : if (req_1 == 1'b1) begin
state <= #1 GNT2;
gnt_1 <= req_0;
end
GNT2 : if (req_0 == 1'b1) begin
state <= #1 GNT1;
gnt_1 <= req_1;
end
default : state <= #1 IDLE;
endcase
end
endmodule

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@ -1,24 +0,0 @@
module latchp
( input d, clk, en, output reg q );
always @*
if ( en )
q <= d;
endmodule
module latchn
( input d, clk, en, output reg q );
always @*
if ( !en )
q <= d;
endmodule
module latchsr
( input d, clk, en, clr, pre, output reg q );
always @*
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else if ( en )
q <= d;
endmodule

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@ -1,65 +0,0 @@
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
always @(*)
Y = (S)? B : A;
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
4 : Y = D[4];
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule

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@ -1,16 +0,0 @@
module top (
out,
clk,
in
);
output [7:0] out;
input signed clk, in;
reg signed [7:0] out = 0;
always @(posedge clk)
begin
out <= out >> 1;
out[7] <= in;
end
endmodule

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@ -1,8 +0,0 @@
module tristate (en, i, o);
input en;
input i;
output o;
assign o = en ? i : 1'bz;
endmodule

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@ -1,4 +1,4 @@
read_verilog add_sub.v
read_verilog ../common/add_sub.v
hierarchy -top top
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check

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@ -1,4 +1,4 @@
read_verilog counter.v
read_verilog ../common/counter.v
hierarchy -top top
proc
flatten

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@ -1,4 +1,4 @@
read_verilog dffs.v
read_verilog ../common/dffs.v
design -save read
hierarchy -top dff

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@ -1,4 +1,4 @@
read_verilog fsm.v
read_verilog ../common/fsm.v
hierarchy -top fsm
proc
#flatten

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@ -1,4 +1,4 @@
read_verilog latches.v
read_verilog ../common/latches.v
design -save read
hierarchy -top latchp

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@ -0,0 +1,11 @@
read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT1
select -assert-count 6 t:AL_MAP_LUT2
select -assert-count 2 t:AL_MAP_LUT4
select -assert-none t:AL_MAP_LUT1 t:AL_MAP_LUT2 t:AL_MAP_LUT4 %% t:* %D

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@ -1,4 +1,4 @@
read_verilog memory.v
read_verilog ../common/memory.v
hierarchy -top top
proc
memory -nomap

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@ -1,4 +1,4 @@
read_verilog mux.v
read_verilog ../common/mux.v
design -save read
hierarchy -top mux2

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@ -6,7 +6,7 @@ for x in *.ys; do
echo "all:: run-$x"
echo "run-$x:"
echo " @echo 'Running $x..'"
echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
echo " @../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
done
for s in *.sh; do
if [ "$s" != "run-test.sh" ]; then

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@ -1,4 +1,4 @@
read_verilog shifter.v
read_verilog ../common/shifter.v
hierarchy -top top
proc
flatten

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@ -1,4 +1,4 @@
read_verilog tribuf.v
read_verilog ../common/tribuf.v
hierarchy -top tristate
proc
flatten

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@ -0,0 +1,12 @@
module top
(
input [3:0] x,
input [3:0] y,
output [3:0] A,
output [3:0] B
);
assign A = x + y;
assign B = x - y;
endmodule

43
tests/arch/common/adffs.v Normal file
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@ -0,0 +1,43 @@
module adff( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffs( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnr( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule

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@ -0,0 +1,11 @@
module top ( out, clk, reset );
output [7:0] out;
input clk, reset;
reg [7:0] out;
always @(posedge clk, posedge reset)
if (reset)
out <= 8'b0;
else
out <= out + 1;
endmodule

13
tests/arch/common/dffs.v Normal file
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@ -0,0 +1,13 @@
module dff ( input d, clk, output reg q );
always @( posedge clk )
q <= d;
endmodule
module dffe( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule

51
tests/arch/common/fsm.v Normal file
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@ -0,0 +1,51 @@
module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 );
input clock,reset,req_0,req_1;
output gnt_0,gnt_1;
wire clock,reset,req_0,req_1;
reg gnt_0,gnt_1;
parameter SIZE = 3;
parameter IDLE = 3'b001;
parameter GNT0 = 3'b010;
parameter GNT1 = 3'b100;
parameter GNT2 = 3'b101;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end
else
case(state)
IDLE : if (req_0 == 1'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1 : if (req_1 == 1'b1) begin
state <= #1 GNT2;
gnt_1 <= req_0;
end
GNT2 : if (req_0 == 1'b1) begin
state <= #1 GNT1;
gnt_1 <= req_1;
end
default : state <= #1 IDLE;
endcase
end
endmodule

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@ -1,19 +1,16 @@
module latchp
( input d, clk, en, output reg q );
module latchp ( input d, clk, en, output reg q );
always @*
if ( en )
q <= d;
endmodule
module latchn
( input d, clk, en, output reg q );
module latchn ( input d, clk, en, output reg q );
always @*
if ( !en )
q <= d;
endmodule
module latchsr
( input d, clk, en, clr, pre, output reg q );
module latchsr ( input d, clk, en, clr, pre, output reg q );
always @*
if ( clr )
q <= 1'b0;

16
tests/arch/common/logic.v Normal file
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@ -0,0 +1,16 @@
module top
(
input [0:7] in,
output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
);
assign B1 = in[0] & in[1];
assign B2 = in[0] | in[1];
assign B3 = in[0] ~& in[1];
assign B4 = in[0] ~| in[1];
assign B5 = in[0] ^ in[1];
assign B6 = in[0] ~^ in[1];
assign B7 = ~in[0];
assign B8 = in[0];
assign B9 = in[0:1] && in [2:3];
assign B10 = in[0:1] || in [2:3];
endmodule

9
tests/arch/common/mul.v Normal file
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@ -0,0 +1,9 @@
module top
(
input [5:0] x,
input [5:0] y,
output [11:0] A,
);
assign A = x * y;
endmodule

60
tests/arch/common/mux.v Normal file
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@ -0,0 +1,60 @@
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
always @(*)
Y = (S)? B : A;
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
4 : Y = D[4];
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule

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@ -1,8 +1,4 @@
module top (
out,
clk,
in
);
module top(out, clk, in);
output [7:0] out;
input signed clk, in;
reg signed [7:0] out = 0;
@ -11,6 +7,5 @@ in
begin
out <= out >> 1;
out[7] <= in;
end
end
endmodule

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@ -1,8 +1,8 @@
module tristate (en, i, o);
module tristate(en, i, o);
input en;
input i;
output reg o;
always @(en or i)
o <= (en)? i : 1'bZ;
o <= (en)? i : 1'bZ;
endmodule

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@ -1,4 +1,4 @@
read_verilog add_sub.v
read_verilog ../common/add_sub.v
hierarchy -top top
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check

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@ -1,4 +1,4 @@
read_verilog adffs.v
read_verilog ../common/adffs.v
design -save read
hierarchy -top adff

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@ -1,4 +1,4 @@
read_verilog counter.v
read_verilog ../common/counter.v
hierarchy -top top
proc
flatten

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@ -1,4 +1,4 @@
read_verilog dffs.v
read_verilog ../common/dffs.v
design -save read
hierarchy -top dff

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@ -1,4 +1,4 @@
read_verilog fsm.v
read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten

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@ -1,5 +1,4 @@
read_verilog latches.v
read_verilog ../common/latches.v
design -save read
hierarchy -top latchp

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@ -1,4 +1,4 @@
read_verilog logic.v
read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check

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@ -1,4 +1,4 @@
read_verilog memory.v
read_verilog ../common/memory.v
hierarchy -top top
proc
memory -nomap

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@ -1,4 +1,4 @@
read_verilog mul.v
read_verilog ../common/mul.v
hierarchy -top top
proc
# Blocked by issue #1358 (Missing ECP5 simulation models)

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@ -1,4 +1,4 @@
read_verilog mux.v
read_verilog ../common/mux.v
design -save read
hierarchy -top mux2

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@ -6,7 +6,7 @@ for x in *.ys; do
echo "all:: run-$x"
echo "run-$x:"
echo " @echo 'Running $x..'"
echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
echo " @../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
done
for s in *.sh; do
if [ "$s" != "run-test.sh" ]; then

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@ -1,4 +1,4 @@
read_verilog shifter.v
read_verilog ../common/shifter.v
hierarchy -top top
proc
flatten

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@ -1,4 +1,4 @@
read_verilog tribuf.v
read_verilog ../common/tribuf.v
hierarchy -top tristate
proc
flatten

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@ -1,4 +1,4 @@
read_verilog add_sub.v
read_verilog ../common/add_sub.v
hierarchy -top top
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check

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@ -1,4 +1,4 @@
read_verilog adffs.v
read_verilog ../common/adffs.v
design -save read
hierarchy -top adff

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@ -1,4 +1,4 @@
read_verilog counter.v
read_verilog ../common/counter.v
hierarchy -top top
proc
flatten

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@ -1,4 +1,4 @@
read_verilog dffs.v
read_verilog ../common/dffs.v
design -save read
hierarchy -top dff

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@ -1,4 +1,4 @@
read_verilog fsm.v
read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten

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@ -1,4 +1,4 @@
read_verilog latches.v
read_verilog ../common/latches.v
design -save read
hierarchy -top latchp

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@ -1,4 +1,4 @@
read_verilog logic.v
read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check

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@ -1,4 +1,4 @@
read_verilog memory.v
read_verilog ../common/memory.v
hierarchy -top top
proc
memory -nomap

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@ -1,4 +1,4 @@
read_verilog mux.v
read_verilog ../common/mux.v
design -save read
hierarchy -top mux2

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@ -6,7 +6,7 @@ for x in *.ys; do
echo "all:: run-$x"
echo "run-$x:"
echo " @echo 'Running $x..'"
echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
echo " @../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
done
for s in *.sh; do
if [ "$s" != "run-test.sh" ]; then

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@ -1,4 +1,4 @@
read_verilog shifter.v
read_verilog ../common/shifter.v
hierarchy -top top
proc
flatten

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@ -1,4 +1,4 @@
read_verilog tribuf.v
read_verilog ../common/tribuf.v
hierarchy -top tristate
proc
tribuf

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@ -1,4 +1,4 @@
read_verilog add_sub.v
read_verilog ../common/add_sub.v
hierarchy -top top
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)

39
tests/arch/ice40/adffs.ys Normal file
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@ -0,0 +1,39 @@
read_verilog ../common/adffs.v
design -save read
hierarchy -top adff
proc
equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFFR
select -assert-none t:SB_DFFR %% t:* %D
design -load read
hierarchy -top adffn
proc
equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFFR
select -assert-count 1 t:SB_LUT4
select -assert-none t:SB_DFFR t:SB_LUT4 %% t:* %D
design -load read
hierarchy -top dffs
proc
equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFFSS
select -assert-none t:SB_DFFSS %% t:* %D
design -load read
hierarchy -top ndffnr
proc
equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFFNSR
select -assert-count 1 t:SB_LUT4
select -assert-none t:SB_DFFNSR t:SB_LUT4 %% t:* %D

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@ -1,4 +1,4 @@
read_verilog counter.v
read_verilog ../common/counter.v
hierarchy -top top
proc
flatten

19
tests/arch/ice40/dffs.ys Normal file
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@ -0,0 +1,19 @@
read_verilog ../common/dffs.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D

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@ -1,10 +1,10 @@
read_verilog fsm.v
hierarchy -top top
read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
cd fsm # Constrain all select calls below inside the top module
select -assert-count 2 t:SB_DFFESR
select -assert-count 2 t:SB_DFFSR

View file

@ -0,0 +1,33 @@
read_verilog ../common/latches.v
design -save read
hierarchy -top latchp
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ice40
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D
design -load read
hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ice40
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D
design -load read
hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ice40
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 2 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D

View file

@ -1,4 +1,4 @@
read_verilog logic.v
read_verilog ../common/logic.v
hierarchy -top top
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)

View file

@ -1,4 +1,4 @@
read_verilog memory.v
read_verilog ../common/memory.v
hierarchy -top top
proc
memory -nomap

View file

@ -1,4 +1,4 @@
read_verilog mul.v
read_verilog ../common/mul.v
hierarchy -top top
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)

40
tests/arch/ice40/mux.ys Normal file
View file

@ -0,0 +1,40 @@
read_verilog ../common/mux.v
design -save read
hierarchy -top mux2
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux2 # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D
design -load read
hierarchy -top mux4
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 2 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D
design -load read
hierarchy -top mux8
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 5 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D
design -load read
hierarchy -top mux16
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-count 11 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D

View file

@ -6,7 +6,7 @@ for x in *.ys; do
echo "all:: run-$x"
echo "run-$x:"
echo " @echo 'Running $x..'"
echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
echo " @../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
done
for s in *.sh; do
if [ "$s" != "run-test.sh" ]; then

View file

@ -1,4 +1,4 @@
read_verilog shifter.v
read_verilog ../common/shifter.v
hierarchy -top top
proc
flatten

View file

@ -1,9 +1,11 @@
read_verilog tribuf.v
hierarchy -top top
read_verilog ../common/tribuf.v
hierarchy -top tristate
proc
tribuf
flatten
synth
equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
cd tristate # Constrain all select calls below inside the top module
select -assert-count 1 t:$_TBUF_
select -assert-none t:$_TBUF_ %% t:* %D

View file

@ -1,4 +1,4 @@
read_verilog add_sub.v
read_verilog ../common/add_sub.v
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check

View file

@ -1,4 +1,4 @@
read_verilog adffs.v
read_verilog ../common/adffs.v
design -save read
hierarchy -top adff

View file

@ -1,4 +1,4 @@
read_verilog counter.v
read_verilog ../common/counter.v
hierarchy -top top
proc
flatten

View file

@ -1,4 +1,4 @@
read_verilog dffs.v
read_verilog ../common/dffs.v
design -save read
hierarchy -top dff

View file

@ -1,4 +1,4 @@
read_verilog fsm.v
read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten

View file

@ -1,4 +1,4 @@
read_verilog latches.v
read_verilog ../common/latches.v
design -save read
hierarchy -top latchp

View file

@ -1,4 +1,4 @@
read_verilog logic.v
read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check

View file

@ -0,0 +1,3 @@
../../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" macc.v -o macc_uut.v
iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v
vvp -N ./test_macc

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