mirror of
https://github.com/YosysHQ/yosys
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Merge pull request #1455 from YosysHQ/dave/ultrascaleplus
Add BRAM and URAM mapping for UltraScale[+]
This commit is contained in:
David Shah
GitHub
commit
34dadd9ab2
9 changed files with 1153 additions and 417 deletions
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@ -32,9 +32,13 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_cells_xtra.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_bb.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_xcu_brams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_brams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_brams_bb.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcup_urams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcup_urams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
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@ -228,8 +228,8 @@ XC6V_CELLS = [
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# Cell('FDSE'),
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Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}),
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Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
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Cell('LDCE'),
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Cell('LDPE'),
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# Cell('LDCE'),
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# Cell('LDPE'),
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Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}),
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# Slice/CLB primitives.
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@ -378,8 +378,8 @@ XC7_CELLS = [
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# Cell('FDSE'),
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Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}),
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Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
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Cell('LDCE'),
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Cell('LDPE'),
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# Cell('LDCE'),
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# Cell('LDPE'),
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Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}),
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# Slice/CLB primitives.
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@ -435,8 +435,8 @@ XCU_CELLS = [
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# Blockram.
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Cell('FIFO18E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
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Cell('FIFO36E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
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Cell('RAMB18E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
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Cell('RAMB36E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
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#Cell('RAMB18E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
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#Cell('RAMB36E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
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Cell('URAM288', port_attrs={'CLK': ['clkbuf_sink']}),
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Cell('URAM288_BASE', port_attrs={'CLK': ['clkbuf_sink']}),
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@ -491,6 +491,12 @@ XCU_CELLS = [
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Cell('PLLE3_BASE'),
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Cell('PLLE4_ADV'),
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Cell('PLLE4_BASE'),
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# the "E2" variants are not strictly speaking UltraScale[+] cells
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# but are automatically upgraded for backwards compatibility purposes
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Cell('MMCME2_ADV'),
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Cell('MMCME2_BASE'),
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Cell('PLLE2_ADV'),
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Cell('PLLE2_BASE'),
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# Configuration.
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Cell('BSCANE2', keep=True),
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@ -562,8 +568,8 @@ XCU_CELLS = [
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# Cell('FDSE'),
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Cell('HARD_SYNC', port_attrs={'CLK': ['clkbuf_sink']}),
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Cell('IDDRE1', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
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Cell('LDCE'),
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Cell('LDPE'),
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# Cell('LDCE'),
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# Cell('LDPE'),
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Cell('ODDRE1', port_attrs={'C': ['clkbuf_sink']}),
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# NOTE: not in the official library guide!
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@ -93,6 +93,9 @@ struct SynthXilinxPass : public ScriptPass
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log(" -noclkbuf\n");
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log(" disable automatic clock buffer insertion\n");
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log("\n");
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log(" -uram\n");
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log(" infer URAM288s for large memories (xcup only)\n");
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log("\n");
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log(" -widemux <int>\n");
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log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n");
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log(" above this number of inputs (minimum value 2, recommended value >= 5).\n");
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@ -119,7 +122,7 @@ struct SynthXilinxPass : public ScriptPass
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}
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std::string top_opt, edif_file, blif_file, family;
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bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, abc9;
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bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram, abc9;
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bool flatten_before_abc;
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int widemux;
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@ -143,6 +146,7 @@ struct SynthXilinxPass : public ScriptPass
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nocarry = false;
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nowidelut = false;
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nodsp = false;
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uram = false;
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abc9 = false;
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flatten_before_abc = false;
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widemux = 0;
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@ -248,6 +252,10 @@ struct SynthXilinxPass : public ScriptPass
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nodsp = true;
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continue;
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}
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if (args[argidx] == "-uram") {
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uram = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -305,6 +313,8 @@ struct SynthXilinxPass : public ScriptPass
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run("read_verilog -lib +/xilinx/xc6s_brams_bb.v");
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} else if (family == "xc6v" || family == "xc7") {
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run("read_verilog -lib +/xilinx/xc7_brams_bb.v");
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} else if (family == "xcu" || family == "xcup") {
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run("read_verilog -lib +/xilinx/xcu_brams_bb.v");
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}
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run(stringf("hierarchy -check %s", top_opt.c_str()));
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@ -408,6 +418,20 @@ struct SynthXilinxPass : public ScriptPass
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run("opt_clean");
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}
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if (check_label("map_uram", "(only if '-uram')")) {
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if (help_mode) {
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run("memory_bram -rules +/xilinx/{family}_urams.txt");
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run("techmap -map +/xilinx/{family}_urams_map.v");
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} else if (uram) {
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if (family == "xcup") {
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run("memory_bram -rules +/xilinx/xcup_urams.txt");
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run("techmap -map +/xilinx/xcup_urams_map.v");
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} else {
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log_warning("UltraRAM inference not supported for family %s.\n", family.c_str());
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}
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}
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}
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if (check_label("map_bram", "(skip if '-nobram')")) {
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if (help_mode) {
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run("memory_bram -rules +/xilinx/{family}_brams.txt");
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@ -417,8 +441,11 @@ struct SynthXilinxPass : public ScriptPass
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run("memory_bram -rules +/xilinx/xc6s_brams.txt");
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run("techmap -map +/xilinx/xc6s_brams_map.v");
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} else if (family == "xc6v" || family == "xc7") {
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run("memory_bram -rules +/xilinx/xc7_brams.txt");
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run("memory_bram -rules +/xilinx/xc7_xcu_brams.txt");
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run("techmap -map +/xilinx/xc7_brams_map.v");
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} else if (family == "xcu" || family == "xcup") {
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run("memory_bram -rules +/xilinx/xc7_xcu_brams.txt");
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run("techmap -map +/xilinx/xcu_brams_map.v");
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} else {
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log_warning("Block RAM inference not yet supported for family %s.\n", family.c_str());
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}
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405
techlibs/xilinx/xcu_brams_bb.v
Normal file
405
techlibs/xilinx/xcu_brams_bb.v
Normal file
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@ -0,0 +1,405 @@
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module RAMB18E2 (...);
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parameter CASCADE_ORDER_A = "NONE";
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parameter CASCADE_ORDER_B = "NONE";
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parameter CLOCK_DOMAINS = "INDEPENDENT";
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parameter integer DOA_REG = 1;
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parameter integer DOB_REG = 1;
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parameter ENADDRENA = "FALSE";
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parameter ENADDRENB = "FALSE";
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parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [17:0] INIT_A = 18'h00000;
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parameter [17:0] INIT_B = 18'h00000;
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parameter INIT_FILE = "NONE";
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parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0;
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parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0;
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parameter [0:0] IS_ENARDEN_INVERTED = 1'b0;
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parameter [0:0] IS_ENBWREN_INVERTED = 1'b0;
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parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0;
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parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0;
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parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0;
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parameter [0:0] IS_RSTREGB_INVERTED = 1'b0;
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parameter RDADDRCHANGEA = "FALSE";
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parameter RDADDRCHANGEB = "FALSE";
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parameter integer READ_WIDTH_A = 0;
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parameter integer READ_WIDTH_B = 0;
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parameter RSTREG_PRIORITY_A = "RSTREG";
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parameter RSTREG_PRIORITY_B = "RSTREG";
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parameter SIM_COLLISION_CHECK = "ALL";
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parameter SLEEP_ASYNC = "FALSE";
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parameter [17:0] SRVAL_A = 18'h00000;
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parameter [17:0] SRVAL_B = 18'h00000;
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parameter WRITE_MODE_A = "NO_CHANGE";
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parameter WRITE_MODE_B = "NO_CHANGE";
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parameter integer WRITE_WIDTH_A = 0;
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parameter integer WRITE_WIDTH_B = 0;
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output [15:0] CASDOUTA;
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output [15:0] CASDOUTB;
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output [1:0] CASDOUTPA;
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output [1:0] CASDOUTPB;
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output [15:0] DOUTADOUT;
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output [15:0] DOUTBDOUT;
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output [1:0] DOUTPADOUTP;
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output [1:0] DOUTPBDOUTP;
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input [13:0] ADDRARDADDR;
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input [13:0] ADDRBWRADDR;
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input ADDRENA;
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input ADDRENB;
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input CASDIMUXA;
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input CASDIMUXB;
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input [15:0] CASDINA;
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input [15:0] CASDINB;
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input [1:0] CASDINPA;
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input [1:0] CASDINPB;
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input CASDOMUXA;
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input CASDOMUXB;
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input CASDOMUXEN_A;
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input CASDOMUXEN_B;
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input CASOREGIMUXA;
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input CASOREGIMUXB;
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input CASOREGIMUXEN_A;
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input CASOREGIMUXEN_B;
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(* clkbuf_sink *)
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(* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
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input CLKARDCLK;
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(* clkbuf_sink *)
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(* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
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input CLKBWRCLK;
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input [15:0] DINADIN;
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input [15:0] DINBDIN;
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input [1:0] DINPADINP;
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input [1:0] DINPBDINP;
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(* invertible_pin = "IS_ENARDEN_INVERTED" *)
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input ENARDEN;
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(* invertible_pin = "IS_ENBWREN_INVERTED" *)
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input ENBWREN;
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input REGCEAREGCE;
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input REGCEB;
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(* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
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input RSTRAMARSTRAM;
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(* invertible_pin = "IS_RSTRAMB_INVERTED" *)
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input RSTRAMB;
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(* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
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input RSTREGARSTREG;
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(* invertible_pin = "IS_RSTREGB_INVERTED" *)
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input RSTREGB;
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input SLEEP;
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input [1:0] WEA;
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input [3:0] WEBWE;
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endmodule
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module RAMB36E2 (...);
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parameter CASCADE_ORDER_A = "NONE";
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parameter CASCADE_ORDER_B = "NONE";
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parameter CLOCK_DOMAINS = "INDEPENDENT";
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parameter integer DOA_REG = 1;
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parameter integer DOB_REG = 1;
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parameter ENADDRENA = "FALSE";
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parameter ENADDRENB = "FALSE";
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||||
parameter EN_ECC_PIPE = "FALSE";
|
||||
parameter EN_ECC_READ = "FALSE";
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||||
parameter EN_ECC_WRITE = "FALSE";
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||||
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [35:0] INIT_A = 36'h000000000;
|
||||
parameter [35:0] INIT_B = 36'h000000000;
|
||||
parameter INIT_FILE = "NONE";
|
||||
parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_ENARDEN_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_ENBWREN_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_RSTREGB_INVERTED = 1'b0;
|
||||
parameter RDADDRCHANGEA = "FALSE";
|
||||
parameter RDADDRCHANGEB = "FALSE";
|
||||
parameter integer READ_WIDTH_A = 0;
|
||||
parameter integer READ_WIDTH_B = 0;
|
||||
parameter RSTREG_PRIORITY_A = "RSTREG";
|
||||
parameter RSTREG_PRIORITY_B = "RSTREG";
|
||||
parameter SIM_COLLISION_CHECK = "ALL";
|
||||
parameter SLEEP_ASYNC = "FALSE";
|
||||
parameter [35:0] SRVAL_A = 36'h000000000;
|
||||
parameter [35:0] SRVAL_B = 36'h000000000;
|
||||
parameter WRITE_MODE_A = "NO_CHANGE";
|
||||
parameter WRITE_MODE_B = "NO_CHANGE";
|
||||
parameter integer WRITE_WIDTH_A = 0;
|
||||
parameter integer WRITE_WIDTH_B = 0;
|
||||
output [31:0] CASDOUTA;
|
||||
output [31:0] CASDOUTB;
|
||||
output [3:0] CASDOUTPA;
|
||||
output [3:0] CASDOUTPB;
|
||||
output CASOUTDBITERR;
|
||||
output CASOUTSBITERR;
|
||||
output DBITERR;
|
||||
output [31:0] DOUTADOUT;
|
||||
output [31:0] DOUTBDOUT;
|
||||
output [3:0] DOUTPADOUTP;
|
||||
output [3:0] DOUTPBDOUTP;
|
||||
output [7:0] ECCPARITY;
|
||||
output [8:0] RDADDRECC;
|
||||
output SBITERR;
|
||||
input [14:0] ADDRARDADDR;
|
||||
input [14:0] ADDRBWRADDR;
|
||||
input ADDRENA;
|
||||
input ADDRENB;
|
||||
input CASDIMUXA;
|
||||
input CASDIMUXB;
|
||||
input [31:0] CASDINA;
|
||||
input [31:0] CASDINB;
|
||||
input [3:0] CASDINPA;
|
||||
input [3:0] CASDINPB;
|
||||
input CASDOMUXA;
|
||||
input CASDOMUXB;
|
||||
input CASDOMUXEN_A;
|
||||
input CASDOMUXEN_B;
|
||||
input CASINDBITERR;
|
||||
input CASINSBITERR;
|
||||
input CASOREGIMUXA;
|
||||
input CASOREGIMUXB;
|
||||
input CASOREGIMUXEN_A;
|
||||
input CASOREGIMUXEN_B;
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
|
||||
input CLKARDCLK;
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
|
||||
input CLKBWRCLK;
|
||||
input [31:0] DINADIN;
|
||||
input [31:0] DINBDIN;
|
||||
input [3:0] DINPADINP;
|
||||
input [3:0] DINPBDINP;
|
||||
input ECCPIPECE;
|
||||
(* invertible_pin = "IS_ENARDEN_INVERTED" *)
|
||||
input ENARDEN;
|
||||
(* invertible_pin = "IS_ENBWREN_INVERTED" *)
|
||||
input ENBWREN;
|
||||
input INJECTDBITERR;
|
||||
input INJECTSBITERR;
|
||||
input REGCEAREGCE;
|
||||
input REGCEB;
|
||||
(* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
|
||||
input RSTRAMARSTRAM;
|
||||
(* invertible_pin = "IS_RSTRAMB_INVERTED" *)
|
||||
input RSTRAMB;
|
||||
(* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
|
||||
input RSTREGARSTREG;
|
||||
(* invertible_pin = "IS_RSTREGB_INVERTED" *)
|
||||
input RSTREGB;
|
||||
input SLEEP;
|
||||
input [3:0] WEA;
|
||||
input [7:0] WEBWE;
|
||||
endmodule
|
||||
384
techlibs/xilinx/xcu_brams_map.v
Normal file
384
techlibs/xilinx/xcu_brams_map.v
Normal file
|
|
@ -0,0 +1,384 @@
|
|||
module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
parameter [36863:0] INIT = 36864'bx;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [8:0] A1ADDR;
|
||||
output [71:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [8:0] B1ADDR;
|
||||
input [71:0] B1DATA;
|
||||
input [7:0] B1EN;
|
||||
|
||||
wire [15:0] A1ADDR_16 = {A1ADDR, 6'b0};
|
||||
wire [15:0] B1ADDR_16 = {B1ADDR, 6'b0};
|
||||
|
||||
wire [7:0] DIP, DOP;
|
||||
wire [63:0] DI, DO;
|
||||
|
||||
assign A1DATA = { DOP[7], DO[63:56], DOP[6], DO[55:48], DOP[5], DO[47:40], DOP[4], DO[39:32],
|
||||
DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
|
||||
|
||||
assign { DIP[7], DI[63:56], DIP[6], DI[55:48], DIP[5], DI[47:40], DIP[4], DI[39:32],
|
||||
DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
|
||||
|
||||
RAMB36E2 #(
|
||||
.READ_WIDTH_A(72),
|
||||
.WRITE_WIDTH_B(72),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.DOA_REG(0),
|
||||
.DOB_REG(0),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_36.vh"
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DOUTBDOUT(DO[63:32]),
|
||||
.DOUTADOUT(DO[31:0]),
|
||||
.DOUTPBDOUTP(DOP[7:4]),
|
||||
.DOUTPADOUTP(DOP[3:0]),
|
||||
.DINBDIN(DI[63:32]),
|
||||
.DINADIN(DI[31:0]),
|
||||
.DINPBDINP(DIP[7:4]),
|
||||
.DINPADINP(DIP[3:0]),
|
||||
|
||||
.ADDRARDADDR(A1ADDR_16),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.ADDRENA(|1),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(4'b0),
|
||||
|
||||
.ADDRBWRADDR(B1ADDR_16),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.ADDRENB(|1),
|
||||
.REGCEB(|1),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN),
|
||||
|
||||
.SLEEP(|0)
|
||||
);
|
||||
endmodule
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
||||
module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
parameter [18431:0] INIT = 18432'bx;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [8:0] A1ADDR;
|
||||
output [35:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [8:0] B1ADDR;
|
||||
input [35:0] B1DATA;
|
||||
input [3:0] B1EN;
|
||||
|
||||
wire [13:0] A1ADDR_14 = {A1ADDR, 5'b0};
|
||||
wire [13:0] B1ADDR_14 = {B1ADDR, 5'b0};
|
||||
|
||||
wire [3:0] DIP, DOP;
|
||||
wire [31:0] DI, DO;
|
||||
|
||||
assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
|
||||
assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
|
||||
|
||||
RAMB18E2 #(
|
||||
.READ_WIDTH_A(36),
|
||||
.WRITE_WIDTH_B(36),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.DOA_REG(0),
|
||||
.DOB_REG(0),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_18.vh"
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DOUTBDOUT(DO[31:16]),
|
||||
.DOUTADOUT(DO[15:0]),
|
||||
.DOUTPBDOUTP(DOP[3:2]),
|
||||
.DOUTPADOUTP(DOP[1:0]),
|
||||
.DINBDIN(DI[31:16]),
|
||||
.DINADIN(DI[15:0]),
|
||||
.DINPBDINP(DIP[3:2]),
|
||||
.DINPADINP(DIP[1:0]),
|
||||
|
||||
.ADDRARDADDR(A1ADDR_14),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.ADDRENA(|1),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(2'b0),
|
||||
|
||||
.ADDRBWRADDR(B1ADDR_14),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.ADDRENB(|1),
|
||||
.REGCEB(|1),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN),
|
||||
|
||||
.SLEEP(|0)
|
||||
);
|
||||
endmodule
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
||||
module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CFG_ABITS = 10;
|
||||
parameter CFG_DBITS = 36;
|
||||
parameter CFG_ENABLE_B = 4;
|
||||
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
parameter [36863:0] INIT = 36864'bx;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [CFG_ABITS-1:0] A1ADDR;
|
||||
output [CFG_DBITS-1:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [CFG_ABITS-1:0] B1ADDR;
|
||||
input [CFG_DBITS-1:0] B1DATA;
|
||||
input [CFG_ENABLE_B-1:0] B1EN;
|
||||
|
||||
wire [15:0] A1ADDR_16 = A1ADDR << (15 - CFG_ABITS);
|
||||
wire [15:0] B1ADDR_16 = B1ADDR << (15 - CFG_ABITS);
|
||||
wire [7:0] B1EN_8 = B1EN;
|
||||
|
||||
wire [3:0] DIP, DOP;
|
||||
wire [31:0] DI, DO;
|
||||
|
||||
wire [31:0] DOBDO;
|
||||
wire [3:0] DOPBDOP;
|
||||
|
||||
assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
|
||||
assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
|
||||
|
||||
generate if (CFG_DBITS > 8) begin
|
||||
RAMB36E2 #(
|
||||
.READ_WIDTH_A(CFG_DBITS),
|
||||
.READ_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_WIDTH_A(CFG_DBITS),
|
||||
.WRITE_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.DOA_REG(0),
|
||||
.DOB_REG(0),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_36.vh"
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DINADIN(32'hFFFFFFFF),
|
||||
.DINPADINP(4'hF),
|
||||
.DOUTADOUT(DO[31:0]),
|
||||
.DOUTPADOUTP(DOP[3:0]),
|
||||
.ADDRARDADDR(A1ADDR_16),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.ADDRENA(|1),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(4'b0),
|
||||
|
||||
.DINBDIN(DI),
|
||||
.DINPBDINP(DIP),
|
||||
.DOUTBDOUT(DOBDO),
|
||||
.DOUTPBDOUTP(DOPBDOP),
|
||||
.ADDRBWRADDR(B1ADDR_16),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.ADDRENB(|1),
|
||||
.REGCEB(|0),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN_8),
|
||||
|
||||
.SLEEP(|0)
|
||||
);
|
||||
end else begin
|
||||
RAMB36E2 #(
|
||||
.READ_WIDTH_A(CFG_DBITS),
|
||||
.READ_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_WIDTH_A(CFG_DBITS),
|
||||
.WRITE_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.DOA_REG(0),
|
||||
.DOB_REG(0),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_32.vh"
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DINADIN(32'hFFFFFFFF),
|
||||
.DINPADINP(4'hF),
|
||||
.DOUTADOUT(DO[31:0]),
|
||||
.DOUTPADOUTP(DOP[3:0]),
|
||||
.ADDRARDADDR(A1ADDR_16),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.ADDRENA(|1),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(4'b0),
|
||||
|
||||
.DINBDIN(DI),
|
||||
.DINPBDINP(DIP),
|
||||
.DOUTBDOUT(DOBDO),
|
||||
.DOUTPBDOUTP(DOPBDOP),
|
||||
.ADDRBWRADDR(B1ADDR_16),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.ADDRENB(|1),
|
||||
.REGCEB(|0),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN_8),
|
||||
|
||||
.SLEEP(|0)
|
||||
);
|
||||
end endgenerate
|
||||
endmodule
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
||||
module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CFG_ABITS = 10;
|
||||
parameter CFG_DBITS = 18;
|
||||
parameter CFG_ENABLE_B = 2;
|
||||
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
parameter [18431:0] INIT = 18432'bx;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [CFG_ABITS-1:0] A1ADDR;
|
||||
output [CFG_DBITS-1:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [CFG_ABITS-1:0] B1ADDR;
|
||||
input [CFG_DBITS-1:0] B1DATA;
|
||||
input [CFG_ENABLE_B-1:0] B1EN;
|
||||
|
||||
wire [13:0] A1ADDR_14 = A1ADDR << (14 - CFG_ABITS);
|
||||
wire [13:0] B1ADDR_14 = B1ADDR << (14 - CFG_ABITS);
|
||||
wire [3:0] B1EN_4 = B1EN;
|
||||
|
||||
wire [1:0] DIP, DOP;
|
||||
wire [15:0] DI, DO;
|
||||
|
||||
wire [15:0] DOBDO;
|
||||
wire [1:0] DOPBDOP;
|
||||
|
||||
assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
|
||||
assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
|
||||
|
||||
generate if (CFG_DBITS > 8) begin
|
||||
RAMB18E2 #(
|
||||
.READ_WIDTH_A(CFG_DBITS),
|
||||
.READ_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_WIDTH_A(CFG_DBITS),
|
||||
.WRITE_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.DOA_REG(0),
|
||||
.DOB_REG(0),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_18.vh"
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DINADIN(16'hFFFF),
|
||||
.DINPADINP(2'b11),
|
||||
.DOUTADOUT(DO),
|
||||
.DOUTPADOUTP(DOP),
|
||||
.ADDRARDADDR(A1ADDR_14),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.ADDRENA(|1),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(2'b0),
|
||||
|
||||
.DINBDIN(DI),
|
||||
.DINPBDINP(DIP),
|
||||
.DOUTBDOUT(DOBDO),
|
||||
.DOUTPBDOUTP(DOPBDOP),
|
||||
.ADDRBWRADDR(B1ADDR_14),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.ADDRENB(|1),
|
||||
.REGCEB(|0),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN_4),
|
||||
|
||||
.SLEEP(|0)
|
||||
);
|
||||
end else begin
|
||||
RAMB18E2 #(
|
||||
//.RAM_MODE("TDP"),
|
||||
.READ_WIDTH_A(CFG_DBITS),
|
||||
.READ_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_WIDTH_A(CFG_DBITS),
|
||||
.WRITE_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.DOA_REG(0),
|
||||
.DOB_REG(0),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_16.vh"
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DINADIN(16'hFFFF),
|
||||
.DINPADINP(2'b11),
|
||||
.DOUTADOUT(DO),
|
||||
.DOUTPADOUTP(DOP),
|
||||
.ADDRARDADDR(A1ADDR_14),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.ADDRENA(|1),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(2'b0),
|
||||
|
||||
.DINBDIN(DI),
|
||||
.DINPBDINP(DIP),
|
||||
.DOUTBDOUT(DOBDO),
|
||||
.DOUTPBDOUTP(DOPBDOP),
|
||||
.ADDRBWRADDR(B1ADDR_14),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.ADDRENB(|1),
|
||||
.REGCEB(|0),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN_4),
|
||||
|
||||
.SLEEP(|0)
|
||||
);
|
||||
end endgenerate
|
||||
endmodule
|
||||
|
||||
|
|
@ -8330,412 +8330,6 @@ module FIFO36E2 (...);
|
|||
input WREN;
|
||||
endmodule
|
||||
|
||||
module RAMB18E2 (...);
|
||||
parameter CASCADE_ORDER_A = "NONE";
|
||||
parameter CASCADE_ORDER_B = "NONE";
|
||||
parameter CLOCK_DOMAINS = "INDEPENDENT";
|
||||
parameter integer DOA_REG = 1;
|
||||
parameter integer DOB_REG = 1;
|
||||
parameter ENADDRENA = "FALSE";
|
||||
parameter ENADDRENB = "FALSE";
|
||||
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [17:0] INIT_A = 18'h00000;
|
||||
parameter [17:0] INIT_B = 18'h00000;
|
||||
parameter INIT_FILE = "NONE";
|
||||
parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_ENARDEN_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_ENBWREN_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_RSTREGB_INVERTED = 1'b0;
|
||||
parameter RDADDRCHANGEA = "FALSE";
|
||||
parameter RDADDRCHANGEB = "FALSE";
|
||||
parameter integer READ_WIDTH_A = 0;
|
||||
parameter integer READ_WIDTH_B = 0;
|
||||
parameter RSTREG_PRIORITY_A = "RSTREG";
|
||||
parameter RSTREG_PRIORITY_B = "RSTREG";
|
||||
parameter SIM_COLLISION_CHECK = "ALL";
|
||||
parameter SLEEP_ASYNC = "FALSE";
|
||||
parameter [17:0] SRVAL_A = 18'h00000;
|
||||
parameter [17:0] SRVAL_B = 18'h00000;
|
||||
parameter WRITE_MODE_A = "NO_CHANGE";
|
||||
parameter WRITE_MODE_B = "NO_CHANGE";
|
||||
parameter integer WRITE_WIDTH_A = 0;
|
||||
parameter integer WRITE_WIDTH_B = 0;
|
||||
output [15:0] CASDOUTA;
|
||||
output [15:0] CASDOUTB;
|
||||
output [1:0] CASDOUTPA;
|
||||
output [1:0] CASDOUTPB;
|
||||
output [15:0] DOUTADOUT;
|
||||
output [15:0] DOUTBDOUT;
|
||||
output [1:0] DOUTPADOUTP;
|
||||
output [1:0] DOUTPBDOUTP;
|
||||
input [13:0] ADDRARDADDR;
|
||||
input [13:0] ADDRBWRADDR;
|
||||
input ADDRENA;
|
||||
input ADDRENB;
|
||||
input CASDIMUXA;
|
||||
input CASDIMUXB;
|
||||
input [15:0] CASDINA;
|
||||
input [15:0] CASDINB;
|
||||
input [1:0] CASDINPA;
|
||||
input [1:0] CASDINPB;
|
||||
input CASDOMUXA;
|
||||
input CASDOMUXB;
|
||||
input CASDOMUXEN_A;
|
||||
input CASDOMUXEN_B;
|
||||
input CASOREGIMUXA;
|
||||
input CASOREGIMUXB;
|
||||
input CASOREGIMUXEN_A;
|
||||
input CASOREGIMUXEN_B;
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
|
||||
input CLKARDCLK;
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
|
||||
input CLKBWRCLK;
|
||||
input [15:0] DINADIN;
|
||||
input [15:0] DINBDIN;
|
||||
input [1:0] DINPADINP;
|
||||
input [1:0] DINPBDINP;
|
||||
(* invertible_pin = "IS_ENARDEN_INVERTED" *)
|
||||
input ENARDEN;
|
||||
(* invertible_pin = "IS_ENBWREN_INVERTED" *)
|
||||
input ENBWREN;
|
||||
input REGCEAREGCE;
|
||||
input REGCEB;
|
||||
(* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
|
||||
input RSTRAMARSTRAM;
|
||||
(* invertible_pin = "IS_RSTRAMB_INVERTED" *)
|
||||
input RSTRAMB;
|
||||
(* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
|
||||
input RSTREGARSTREG;
|
||||
(* invertible_pin = "IS_RSTREGB_INVERTED" *)
|
||||
input RSTREGB;
|
||||
input SLEEP;
|
||||
input [1:0] WEA;
|
||||
input [3:0] WEBWE;
|
||||
endmodule
|
||||
|
||||
module RAMB36E2 (...);
|
||||
parameter CASCADE_ORDER_A = "NONE";
|
||||
parameter CASCADE_ORDER_B = "NONE";
|
||||
parameter CLOCK_DOMAINS = "INDEPENDENT";
|
||||
parameter integer DOA_REG = 1;
|
||||
parameter integer DOB_REG = 1;
|
||||
parameter ENADDRENA = "FALSE";
|
||||
parameter ENADDRENB = "FALSE";
|
||||
parameter EN_ECC_PIPE = "FALSE";
|
||||
parameter EN_ECC_READ = "FALSE";
|
||||
parameter EN_ECC_WRITE = "FALSE";
|
||||
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter [35:0] INIT_A = 36'h000000000;
|
||||
parameter [35:0] INIT_B = 36'h000000000;
|
||||
parameter INIT_FILE = "NONE";
|
||||
parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_ENARDEN_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_ENBWREN_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_RSTREGB_INVERTED = 1'b0;
|
||||
parameter RDADDRCHANGEA = "FALSE";
|
||||
parameter RDADDRCHANGEB = "FALSE";
|
||||
parameter integer READ_WIDTH_A = 0;
|
||||
parameter integer READ_WIDTH_B = 0;
|
||||
parameter RSTREG_PRIORITY_A = "RSTREG";
|
||||
parameter RSTREG_PRIORITY_B = "RSTREG";
|
||||
parameter SIM_COLLISION_CHECK = "ALL";
|
||||
parameter SLEEP_ASYNC = "FALSE";
|
||||
parameter [35:0] SRVAL_A = 36'h000000000;
|
||||
parameter [35:0] SRVAL_B = 36'h000000000;
|
||||
parameter WRITE_MODE_A = "NO_CHANGE";
|
||||
parameter WRITE_MODE_B = "NO_CHANGE";
|
||||
parameter integer WRITE_WIDTH_A = 0;
|
||||
parameter integer WRITE_WIDTH_B = 0;
|
||||
output [31:0] CASDOUTA;
|
||||
output [31:0] CASDOUTB;
|
||||
output [3:0] CASDOUTPA;
|
||||
output [3:0] CASDOUTPB;
|
||||
output CASOUTDBITERR;
|
||||
output CASOUTSBITERR;
|
||||
output DBITERR;
|
||||
output [31:0] DOUTADOUT;
|
||||
output [31:0] DOUTBDOUT;
|
||||
output [3:0] DOUTPADOUTP;
|
||||
output [3:0] DOUTPBDOUTP;
|
||||
output [7:0] ECCPARITY;
|
||||
output [8:0] RDADDRECC;
|
||||
output SBITERR;
|
||||
input [14:0] ADDRARDADDR;
|
||||
input [14:0] ADDRBWRADDR;
|
||||
input ADDRENA;
|
||||
input ADDRENB;
|
||||
input CASDIMUXA;
|
||||
input CASDIMUXB;
|
||||
input [31:0] CASDINA;
|
||||
input [31:0] CASDINB;
|
||||
input [3:0] CASDINPA;
|
||||
input [3:0] CASDINPB;
|
||||
input CASDOMUXA;
|
||||
input CASDOMUXB;
|
||||
input CASDOMUXEN_A;
|
||||
input CASDOMUXEN_B;
|
||||
input CASINDBITERR;
|
||||
input CASINSBITERR;
|
||||
input CASOREGIMUXA;
|
||||
input CASOREGIMUXB;
|
||||
input CASOREGIMUXEN_A;
|
||||
input CASOREGIMUXEN_B;
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
|
||||
input CLKARDCLK;
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
|
||||
input CLKBWRCLK;
|
||||
input [31:0] DINADIN;
|
||||
input [31:0] DINBDIN;
|
||||
input [3:0] DINPADINP;
|
||||
input [3:0] DINPBDINP;
|
||||
input ECCPIPECE;
|
||||
(* invertible_pin = "IS_ENARDEN_INVERTED" *)
|
||||
input ENARDEN;
|
||||
(* invertible_pin = "IS_ENBWREN_INVERTED" *)
|
||||
input ENBWREN;
|
||||
input INJECTDBITERR;
|
||||
input INJECTSBITERR;
|
||||
input REGCEAREGCE;
|
||||
input REGCEB;
|
||||
(* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
|
||||
input RSTRAMARSTRAM;
|
||||
(* invertible_pin = "IS_RSTRAMB_INVERTED" *)
|
||||
input RSTRAMB;
|
||||
(* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
|
||||
input RSTREGARSTREG;
|
||||
(* invertible_pin = "IS_RSTREGB_INVERTED" *)
|
||||
input RSTREGB;
|
||||
input SLEEP;
|
||||
input [3:0] WEA;
|
||||
input [7:0] WEBWE;
|
||||
endmodule
|
||||
|
||||
module URAM288 (...);
|
||||
parameter integer AUTO_SLEEP_LATENCY = 8;
|
||||
parameter integer AVG_CONS_INACTIVE_CYCLES = 10;
|
||||
|
|
@ -9767,6 +9361,256 @@ module PLLE4_BASE (...);
|
|||
input RST;
|
||||
endmodule
|
||||
|
||||
module MMCME2_ADV (...);
|
||||
parameter BANDWIDTH = "OPTIMIZED";
|
||||
parameter real CLKFBOUT_MULT_F = 5.000;
|
||||
parameter real CLKFBOUT_PHASE = 0.000;
|
||||
parameter CLKFBOUT_USE_FINE_PS = "FALSE";
|
||||
parameter real CLKIN1_PERIOD = 0.000;
|
||||
parameter real CLKIN2_PERIOD = 0.000;
|
||||
parameter real CLKIN_FREQ_MAX = 1066.000;
|
||||
parameter real CLKIN_FREQ_MIN = 10.000;
|
||||
parameter real CLKOUT0_DIVIDE_F = 1.000;
|
||||
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT0_PHASE = 0.000;
|
||||
parameter CLKOUT0_USE_FINE_PS = "FALSE";
|
||||
parameter integer CLKOUT1_DIVIDE = 1;
|
||||
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT1_PHASE = 0.000;
|
||||
parameter CLKOUT1_USE_FINE_PS = "FALSE";
|
||||
parameter integer CLKOUT2_DIVIDE = 1;
|
||||
parameter real CLKOUT2_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT2_PHASE = 0.000;
|
||||
parameter CLKOUT2_USE_FINE_PS = "FALSE";
|
||||
parameter integer CLKOUT3_DIVIDE = 1;
|
||||
parameter real CLKOUT3_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT3_PHASE = 0.000;
|
||||
parameter CLKOUT3_USE_FINE_PS = "FALSE";
|
||||
parameter CLKOUT4_CASCADE = "FALSE";
|
||||
parameter integer CLKOUT4_DIVIDE = 1;
|
||||
parameter real CLKOUT4_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT4_PHASE = 0.000;
|
||||
parameter CLKOUT4_USE_FINE_PS = "FALSE";
|
||||
parameter integer CLKOUT5_DIVIDE = 1;
|
||||
parameter real CLKOUT5_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT5_PHASE = 0.000;
|
||||
parameter CLKOUT5_USE_FINE_PS = "FALSE";
|
||||
parameter integer CLKOUT6_DIVIDE = 1;
|
||||
parameter real CLKOUT6_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT6_PHASE = 0.000;
|
||||
parameter CLKOUT6_USE_FINE_PS = "FALSE";
|
||||
parameter real CLKPFD_FREQ_MAX = 550.000;
|
||||
parameter real CLKPFD_FREQ_MIN = 10.000;
|
||||
parameter COMPENSATION = "ZHOLD";
|
||||
parameter integer DIVCLK_DIVIDE = 1;
|
||||
parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_PSEN_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
||||
parameter real REF_JITTER1 = 0.010;
|
||||
parameter real REF_JITTER2 = 0.010;
|
||||
parameter SS_EN = "FALSE";
|
||||
parameter SS_MODE = "CENTER_HIGH";
|
||||
parameter integer SS_MOD_PERIOD = 10000;
|
||||
parameter STARTUP_WAIT = "FALSE";
|
||||
parameter real VCOCLK_FREQ_MAX = 1600.000;
|
||||
parameter real VCOCLK_FREQ_MIN = 600.000;
|
||||
parameter STARTUP_WAIT = "FALSE";
|
||||
output CLKFBOUT;
|
||||
output CLKFBOUTB;
|
||||
output CLKFBSTOPPED;
|
||||
output CLKINSTOPPED;
|
||||
output CLKOUT0;
|
||||
output CLKOUT0B;
|
||||
output CLKOUT1;
|
||||
output CLKOUT1B;
|
||||
output CLKOUT2;
|
||||
output CLKOUT2B;
|
||||
output CLKOUT3;
|
||||
output CLKOUT3B;
|
||||
output CLKOUT4;
|
||||
output CLKOUT5;
|
||||
output CLKOUT6;
|
||||
output [15:0] DO;
|
||||
output DRDY;
|
||||
output LOCKED;
|
||||
output PSDONE;
|
||||
input CLKFBIN;
|
||||
input CLKIN1;
|
||||
input CLKIN2;
|
||||
(* invertible_pin = "IS_CLKINSEL_INVERTED" *)
|
||||
input CLKINSEL;
|
||||
input [6:0] DADDR;
|
||||
input DCLK;
|
||||
input DEN;
|
||||
input [15:0] DI;
|
||||
input DWE;
|
||||
input PSCLK;
|
||||
(* invertible_pin = "IS_PSEN_INVERTED" *)
|
||||
input PSEN;
|
||||
(* invertible_pin = "IS_PSINCDEC_INVERTED" *)
|
||||
input PSINCDEC;
|
||||
(* invertible_pin = "IS_PWRDWN_INVERTED" *)
|
||||
input PWRDWN;
|
||||
(* invertible_pin = "IS_RST_INVERTED" *)
|
||||
input RST;
|
||||
endmodule
|
||||
|
||||
module MMCME2_BASE (...);
|
||||
parameter BANDWIDTH = "OPTIMIZED";
|
||||
parameter real CLKFBOUT_MULT_F = 5.000;
|
||||
parameter real CLKFBOUT_PHASE = 0.000;
|
||||
parameter real CLKIN1_PERIOD = 0.000;
|
||||
parameter real CLKOUT0_DIVIDE_F = 1.000;
|
||||
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT0_PHASE = 0.000;
|
||||
parameter integer CLKOUT1_DIVIDE = 1;
|
||||
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT1_PHASE = 0.000;
|
||||
parameter integer CLKOUT2_DIVIDE = 1;
|
||||
parameter real CLKOUT2_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT2_PHASE = 0.000;
|
||||
parameter integer CLKOUT3_DIVIDE = 1;
|
||||
parameter real CLKOUT3_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT3_PHASE = 0.000;
|
||||
parameter CLKOUT4_CASCADE = "FALSE";
|
||||
parameter integer CLKOUT4_DIVIDE = 1;
|
||||
parameter real CLKOUT4_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT4_PHASE = 0.000;
|
||||
parameter integer CLKOUT5_DIVIDE = 1;
|
||||
parameter real CLKOUT5_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT5_PHASE = 0.000;
|
||||
parameter integer CLKOUT6_DIVIDE = 1;
|
||||
parameter real CLKOUT6_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT6_PHASE = 0.000;
|
||||
parameter integer DIVCLK_DIVIDE = 1;
|
||||
parameter real REF_JITTER1 = 0.010;
|
||||
parameter STARTUP_WAIT = "FALSE";
|
||||
output CLKFBOUT;
|
||||
output CLKFBOUTB;
|
||||
output CLKOUT0;
|
||||
output CLKOUT0B;
|
||||
output CLKOUT1;
|
||||
output CLKOUT1B;
|
||||
output CLKOUT2;
|
||||
output CLKOUT2B;
|
||||
output CLKOUT3;
|
||||
output CLKOUT3B;
|
||||
output CLKOUT4;
|
||||
output CLKOUT5;
|
||||
output CLKOUT6;
|
||||
output LOCKED;
|
||||
input CLKFBIN;
|
||||
input CLKIN1;
|
||||
input PWRDWN;
|
||||
input RST;
|
||||
endmodule
|
||||
|
||||
module PLLE2_ADV (...);
|
||||
parameter BANDWIDTH = "OPTIMIZED";
|
||||
parameter COMPENSATION = "ZHOLD";
|
||||
parameter STARTUP_WAIT = "FALSE";
|
||||
parameter integer CLKOUT0_DIVIDE = 1;
|
||||
parameter integer CLKOUT1_DIVIDE = 1;
|
||||
parameter integer CLKOUT2_DIVIDE = 1;
|
||||
parameter integer CLKOUT3_DIVIDE = 1;
|
||||
parameter integer CLKOUT4_DIVIDE = 1;
|
||||
parameter integer CLKOUT5_DIVIDE = 1;
|
||||
parameter integer DIVCLK_DIVIDE = 1;
|
||||
parameter integer CLKFBOUT_MULT = 5;
|
||||
parameter real CLKFBOUT_PHASE = 0.000;
|
||||
parameter real CLKIN1_PERIOD = 0.000;
|
||||
parameter real CLKIN2_PERIOD = 0.000;
|
||||
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT0_PHASE = 0.000;
|
||||
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT1_PHASE = 0.000;
|
||||
parameter real CLKOUT2_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT2_PHASE = 0.000;
|
||||
parameter real CLKOUT3_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT3_PHASE = 0.000;
|
||||
parameter real CLKOUT4_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT4_PHASE = 0.000;
|
||||
parameter real CLKOUT5_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT5_PHASE = 0.000;
|
||||
parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
||||
parameter real REF_JITTER1 = 0.010;
|
||||
parameter real REF_JITTER2 = 0.010;
|
||||
parameter real VCOCLK_FREQ_MAX = 2133.000;
|
||||
parameter real VCOCLK_FREQ_MIN = 800.000;
|
||||
parameter real CLKIN_FREQ_MAX = 1066.000;
|
||||
parameter real CLKIN_FREQ_MIN = 19.000;
|
||||
parameter real CLKPFD_FREQ_MAX = 550.0;
|
||||
parameter real CLKPFD_FREQ_MIN = 19.0;
|
||||
output CLKFBOUT;
|
||||
output CLKOUT0;
|
||||
output CLKOUT1;
|
||||
output CLKOUT2;
|
||||
output CLKOUT3;
|
||||
output CLKOUT4;
|
||||
output CLKOUT5;
|
||||
output DRDY;
|
||||
output LOCKED;
|
||||
output [15:0] DO;
|
||||
input CLKFBIN;
|
||||
input CLKIN1;
|
||||
input CLKIN2;
|
||||
(* invertible_pin = "IS_CLKINSEL_INVERTED" *)
|
||||
input CLKINSEL;
|
||||
input DCLK;
|
||||
input DEN;
|
||||
input DWE;
|
||||
(* invertible_pin = "IS_PWRDWN_INVERTED" *)
|
||||
input PWRDWN;
|
||||
(* invertible_pin = "IS_RST_INVERTED" *)
|
||||
input RST;
|
||||
input [15:0] DI;
|
||||
input [6:0] DADDR;
|
||||
endmodule
|
||||
|
||||
module PLLE2_BASE (...);
|
||||
parameter BANDWIDTH = "OPTIMIZED";
|
||||
parameter integer CLKFBOUT_MULT = 5;
|
||||
parameter real CLKFBOUT_PHASE = 0.000;
|
||||
parameter real CLKIN1_PERIOD = 0.000;
|
||||
parameter integer CLKOUT0_DIVIDE = 1;
|
||||
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT0_PHASE = 0.000;
|
||||
parameter integer CLKOUT1_DIVIDE = 1;
|
||||
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT1_PHASE = 0.000;
|
||||
parameter integer CLKOUT2_DIVIDE = 1;
|
||||
parameter real CLKOUT2_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT2_PHASE = 0.000;
|
||||
parameter integer CLKOUT3_DIVIDE = 1;
|
||||
parameter real CLKOUT3_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT3_PHASE = 0.000;
|
||||
parameter integer CLKOUT4_DIVIDE = 1;
|
||||
parameter real CLKOUT4_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT4_PHASE = 0.000;
|
||||
parameter integer CLKOUT5_DIVIDE = 1;
|
||||
parameter real CLKOUT5_DUTY_CYCLE = 0.500;
|
||||
parameter real CLKOUT5_PHASE = 0.000;
|
||||
parameter integer DIVCLK_DIVIDE = 1;
|
||||
parameter real REF_JITTER1 = 0.010;
|
||||
parameter STARTUP_WAIT = "FALSE";
|
||||
output CLKFBOUT;
|
||||
output CLKOUT0;
|
||||
output CLKOUT1;
|
||||
output CLKOUT2;
|
||||
output CLKOUT3;
|
||||
output CLKOUT4;
|
||||
output CLKOUT5;
|
||||
output LOCKED;
|
||||
input CLKFBIN;
|
||||
input CLKIN1;
|
||||
input PWRDWN;
|
||||
input RST;
|
||||
endmodule
|
||||
|
||||
(* keep *)
|
||||
module BSCANE2 (...);
|
||||
parameter DISABLE_JTAG = "FALSE";
|
||||
|
|
|
|||
19
techlibs/xilinx/xcup_urams.txt
Normal file
19
techlibs/xilinx/xcup_urams.txt
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
bram $__XILINX_URAM288
|
||||
init 0
|
||||
abits 12
|
||||
dbits 72
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 0 1
|
||||
enable 1 9
|
||||
transp 0 0
|
||||
clocks 2 2
|
||||
clkpol 2 2
|
||||
endbram
|
||||
|
||||
match $__XILINX_URAM288
|
||||
min bits 131072
|
||||
min efficiency 15
|
||||
shuffle_enable B
|
||||
make_transp
|
||||
endmatch
|
||||
47
techlibs/xilinx/xcup_urams_map.v
Normal file
47
techlibs/xilinx/xcup_urams_map.v
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
module \$__XILINX_URAM288 (CLK2, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CLKPOL2 = 1;
|
||||
|
||||
input CLK2;
|
||||
|
||||
input [11:0] A1ADDR;
|
||||
output [71:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [11:0] B1ADDR;
|
||||
input [71:0] B1DATA;
|
||||
input [8:0] B1EN;
|
||||
|
||||
|
||||
URAM288 #(
|
||||
.BWE_MODE_A("PARITY_INDEPENDENT"),
|
||||
.BWE_MODE_B("PARITY_INDEPENDENT"),
|
||||
.EN_AUTO_SLEEP_MODE("FALSE"),
|
||||
.IREG_PRE_A("FALSE"),
|
||||
.IREG_PRE_B("FALSE"),
|
||||
.IS_CLK_INVERTED(!CLKPOL2),
|
||||
.OREG_A("FALSE"),
|
||||
.OREG_B("FALSE")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.ADDR_A({11'b0, A1ADDR}),
|
||||
.BWE_A(9'b0),
|
||||
.DIN_A(72'b0),
|
||||
.EN_A(A1EN),
|
||||
.RDB_WR_A(1'b0),
|
||||
.INJECT_DBITERR_A(1'b0),
|
||||
.INJECT_SBITERR_A(1'b0),
|
||||
.RST_A(1'b0),
|
||||
.DOUT_A(A1DATA),
|
||||
|
||||
.ADDR_B({11'b0, B1ADDR}),
|
||||
.BWE_B(B1EN),
|
||||
.DIN_B(B1DATA),
|
||||
.EN_B(|B1EN),
|
||||
.RDB_WR_B(1'b1),
|
||||
.INJECT_DBITERR_B(1'b0),
|
||||
.INJECT_SBITERR_B(1'b0),
|
||||
.RST_B(1'b0),
|
||||
|
||||
.CLK(CLK2),
|
||||
.SLEEP(1'b0)
|
||||
);
|
||||
endmodule
|
||||
Loading…
Add table
Add a link
Reference in a new issue