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Author	SHA1	Message	Date
Eddie Hung	48c424e45b	Cleanup	2019-08-23 13:46:05 -07:00
Eddie Hung	e658d472c8	Put attributes above port	2019-08-23 11:31:20 -07:00
Eddie Hung	d672b1ddec	Merge remote-tracking branch 'origin/master' into xaig_arrival	2019-08-23 11:26:55 -07:00
Eddie Hung	509c353fe9	Forgot one	2019-08-23 11:23:50 -07:00
Eddie Hung	a270af00cc	Put abc_* attributes above port	2019-08-23 11:21:44 -07:00
Eddie Hung	bb2d5bc4f8	Merge pull request #1326 from mmicko/doc-update ... Make macOS dependency clear	2019-08-23 09:12:58 -07:00
Miodrag Milanovic	c618ae43b9	Make macOS depenency clear	2019-08-23 10:37:50 +02:00
Eddie Hung	fe1b2337fd	Do not propagate mem2reg attribute through to result	2019-08-22 16:57:59 -07:00
Eddie Hung	c50d68653d	Spelling	2019-08-22 16:06:36 -07:00
Eddie Hung	2fe35f902b	Merge pull request #1322 from mmicko/pyosys_osx ... do not require boost if pyosys is not used	2019-08-22 11:53:27 -07:00
Miodrag Milanovic	e5dac8096d	do not require boost if pyosys is not used	2019-08-22 20:43:52 +02:00
Eddie Hung	926cd10350	Merge pull request #1319 from TeaEngineering/shuckc/brew-tcl-tk ... require tcl-tk in Brewfile	2019-08-22 11:32:44 -07:00
Eddie Hung	b800059fc1	Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx ... opt_expr to trim A port of $shiftx/$shift	2019-08-22 10:31:27 -07:00
Clifford Wolf	e9f3eb9760	Bump year in copyright notice ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-22 18:43:16 +02:00
Clifford Wolf	151db528e4	Fix missing newline at end of file ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-22 18:09:37 +02:00
Clifford Wolf	2c8c8b3c74	Merge pull request #1289 from mmicko/anlogic_fixes ... Anlogic fixes and optimization	2019-08-22 18:09:10 +02:00
Clifford Wolf	4c449caf9b	Fix missing newline at end of file ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-22 18:06:36 +02:00
Clifford Wolf	4d37710e82	Merge pull request #1281 from mmicko/efinix ... Initial support for Efinix Trion series FPGAs	2019-08-22 18:06:02 +02:00
Eddie Hung	9245f0d3f5	Copy-paste typo	2019-08-22 08:43:44 -07:00
Chris Shucksmith	d0322e9584	require tcl-tk in Brewfile	2019-08-22 16:37:40 +01:00
Eddie Hung	6f971470f8	Respect opt_expr -keepdc as per @cliffordwolf	2019-08-22 08:37:27 -07:00
Eddie Hung	379f33af54	Handle $shift and Y_WIDTH > 1 as per @cliffordwolf	2019-08-22 08:22:23 -07:00
Eddie Hung	9e31f01b34	Add cover()	2019-08-22 08:06:24 -07:00
Eddie Hung	d0ffe7544c	Canonical form	2019-08-22 08:05:01 -07:00
Clifford Wolf	34a7c0209d	Merge pull request #1316 from YosysHQ/eddie/fix_mem2reg ... mem2reg to preserve user attributes and src	2019-08-22 10:24:42 +02:00
Eddie Hung	bb1a8a0190	Add test	2019-08-21 21:58:20 -07:00
Eddie Hung	d3a212ff91	opt_expr to trim A port of $shiftx if Y_WIDTH == 1	2019-08-21 21:53:55 -07:00
whitequark	841903582f	Merge pull request #1315 from mmicko/fix_dependencies ... Fix test_pmgen deps	2019-08-21 21:40:31 +00:00
Eddie Hung	a6776ee35e	mem2reg to preserve user attributes and src	2019-08-21 13:36:01 -07:00
Eddie Hung	c7af71ecde	Use semicolon	2019-08-21 11:47:17 -07:00
Eddie Hung	5d0f6cbd54	techmap before read	2019-08-21 11:47:06 -07:00
Eddie Hung	d4d692989a	Merge remote-tracking branch 'origin/master' into xaig_arrival	2019-08-21 11:39:20 -07:00
Eddie Hung	8f69be9cc7	Merge remote-tracking branch 'origin/master' into xaig_arrival	2019-08-21 11:39:14 -07:00
Eddie Hung	399ac760ff	Output "h" extension only if boxes	2019-08-21 11:31:18 -07:00
Eddie Hung	8f0c1232d7	Revert "Fix omode which inserts an output if none exists (otherwise abc9 breaks)" ... This reverts commit 8182cb9d91.	2019-08-21 11:29:40 -07:00
Eddie Hung	584c680691	Add abc_arrival to SRL*	2019-08-21 11:27:42 -07:00
Miodrag Milanovic	948b6f91a1	Fix test_pmgen deps	2019-08-21 17:00:24 +02:00
Clifford Wolf	7d8db1c053	Merge pull request #1314 from YosysHQ/eddie/fix_techmap ... techmap -max_iter to apply to each module individually	2019-08-21 09:12:56 +02:00
Eddie Hung	8182cb9d91	Fix omode which inserts an output if none exists (otherwise abc9 breaks)	2019-08-20 21:30:16 -07:00
Eddie Hung	4d123b7638	Revert "Only xaig if GetSize(output_bits) > 0" ... This reverts commit 7b646101e9.	2019-08-20 21:22:38 -07:00
Eddie Hung	7b646101e9	Only xaig if GetSize(output_bits) > 0	2019-08-20 20:57:13 -07:00
Eddie Hung	076af2e617	Missing newline	2019-08-20 20:37:52 -07:00
Eddie Hung	9b9d759451	Fix copy-paste typo	2019-08-20 20:18:51 -07:00
Eddie Hung	64d62710de	Oops	2019-08-20 20:07:38 -07:00
Eddie Hung	affe9c9c1a	Merge branch 'eddie/fix_techmap' into xaig_arrival	2019-08-20 20:06:47 -07:00
Eddie Hung	fe61dcce8b	Grammar	2019-08-20 20:05:51 -07:00
Eddie Hung	fce8dc7db2	Add test	2019-08-20 20:05:16 -07:00
Eddie Hung	193eae0c84	techmap -max_iter to apply to each module individually	2019-08-20 19:50:20 -07:00
Eddie Hung	57493e328a	techmap -max_iter to apply to each module individually	2019-08-20 19:48:16 -07:00
Eddie Hung	c26c556384	xilinx to use abc_map.v with -max_iter 1	2019-08-20 19:47:11 -07:00