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Author SHA1 Message Date
Eddie Hung
46ed0db2ec
Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings 
tests: reduce test warnings
 2020-06-03 08:37:07 -07:00
whitequark
577859fbdb
Merge pull request #2104 from whitequark/simplify-techmap 
techmap: simplify
 2020-06-03 12:45:02 +00:00
whitequark
fb5b070e7e techmap: remove dead variable. NFC. 2020-06-03 01:44:06 +00:00
whitequark
0a74368bfc techmap: use C++11 default member initializers. NFC. 2020-06-02 23:43:20 +00:00
whitequark
f3e86bb32a techmap: simplify. 
`rewrite_filename` is already called in `Frontend::extra_args`.
 2020-06-02 23:43:20 +00:00
whitequark
68d747f767 techmap: use +/techmap.v instead of an ad-hoc code generator. 2020-06-02 23:43:20 +00:00
clairexen
4b3f48a7ec
Merge pull request #2102 from YosysHQ/tests_fix 
allow range for mux test
 2020-06-02 17:13:08 +02:00
clairexen
2ed045738b
Merge pull request #2101 from YosysHQ/mmicko/verific_asymmetric 
Support asymmetric memories for verific frontend
 2020-06-02 17:12:02 +02:00
Miodrag Milanovic
0a88f002e5 allow range for mux test 2020-06-01 13:48:19 +02:00
Miodrag Milanovic
71072d1945 Support asymmetric memories for verific frontend 2020-06-01 10:30:03 +02:00
clairexen
ff785cdb46
Merge pull request #1862 from boqwxp/cleanup_techmap 
Clean up `passes/techmap/techmap.cc`
 2020-05-31 20:40:48 +02:00
Eddie Hung
fe273faad1
Merge pull request #2081 from YosysHQ/eddie/blackbox_ast 
blackbox: use Module::makeblackbox() method
 2020-05-30 08:59:20 -07:00
clairexen
ea46ed81f9
Merge pull request #2018 from boqwxp/qbfsat-timeout 
smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.
 2020-05-30 15:04:51 +02:00
Alberto Gonzalez
ea30465107
smtbmc: Remove superfluous yosys-smt2-timeout file macro. 
Co-Authored-By: clairexen <claire@symbioticeda.com>
 2020-05-29 21:33:00 +00:00
clairexen
0a14e1e837
Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic 
ast/simplify: don't bitblast async ROMs declared as `logic`
 2020-05-29 16:52:11 +02:00
clairexen
94c1035389
Merge pull request #1885 from Xiretza/mod-rem-cells 
Fix modulo/remainder semantics
 2020-05-29 16:37:23 +02:00
clairexen
af36afe722
Merge pull request #2092 from whitequark/rtlil-no-space-control 
Restrict RTLIL::IdString to not contain whitespace or control chars
 2020-05-29 16:31:44 +02:00
clairexen
5874a14d65
Merge pull request #2017 from boqwxp/qbfsat-cvc4 
qbfsat: Add support for CVC4.
 2020-05-29 16:23:10 +02:00
clairexen
1c8d5a08a0
Merge pull request #2016 from boqwxp/qbfsat-yices 
qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default.
 2020-05-29 16:21:45 +02:00
whitequark
626c74adbd
Merge pull request #2097 from whitequark/ilang_lexer-fix-erange 
ilang_lexer: fix check for out of range literal
 2020-05-29 09:04:27 +00:00
whitequark
13b2963ded ilang_lexer: fix check for out of range literal. 
Commit ca70a104 did not use a correct check.
 2020-05-29 06:58:44 +00:00
whitequark
2116d9500c
Merge pull request #2033 from boqwxp/cleanup-verilog-lexer 
verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
 2020-05-29 06:46:33 +00:00
whitequark
efa7424fb9 Restrict RTLIL::IdString to not contain whitespace or control chars. 
This is an existing invariant (most backends can't cope with these)
but one that was not checked or documented.
 2020-05-29 06:43:18 +00:00
Xiretza
f88bef7672
Document division and modulo cells 2020-05-28 22:59:04 +02:00
Xiretza
c34cb90a20
Update CHANGELOG 2020-05-28 22:59:04 +02:00
Xiretza
7c89738382
Add comments for mod/div semantics to rtlil.h 2020-05-28 22:59:04 +02:00
Xiretza
6a2bac21d3
Expand tests/simple/constmuldivmod.v 2020-05-28 22:59:04 +02:00
Xiretza
edd8ff2c07
Add flooring division operator 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.

This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
 2020-05-28 22:59:04 +02:00
Xiretza
17163cf43a
Add flooring modulo operator 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).

This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
 2020-05-28 22:59:03 +02:00
whitequark
0d99522b3c
Merge pull request #2095 from rswarbrick/hier-typo 
Fix small typos in documentation for hierarchy command
 2020-05-28 10:49:14 +00:00
Rupert Swarbrick
1158bbf7db Fix small typos in documentation for hierarchy command 2020-05-28 11:39:44 +01:00
whitequark
abac0ab28e
Merge pull request #2091 from boqwxp/printattrs 
Add `printattrs` command to print attributes of currently selected objects.
 2020-05-28 10:25:34 +00:00
whitequark
2384a59e2a
Merge pull request #2051 from Xiretza/makefile-cd-warning 
Suppress warning during initial clone of ABC repo
 2020-05-28 10:00:49 +00:00
whitequark
736ccb2ad5
Merge pull request #2031 from epfl-vlsc/master 
Add extmodule support to firrtl backend
 2020-05-28 09:59:17 +00:00
whitequark
2974183855
Merge pull request #2063 from boqwxp/techmapped-firrtl 
firrtl: Accept techmapped cell types in FIRRTL backend.
 2020-05-28 09:42:58 +00:00
whitequark
02bb52eef1
Merge pull request #2088 from rswarbrick/count-at 
Minor optimisation in Module::wire() and Module::cell()
 2020-05-28 09:41:17 +00:00
whitequark
fdca785eda
Merge pull request #2087 from rswarbrick/lex-warn 
Silence spurious warning in Verilog lexer when compiling with GCC
 2020-05-28 09:41:04 +00:00
whitequark
8a44a46806
Merge pull request #2086 from rswarbrick/sigbit 
Use default copy constructor for RTLIL::SigBit
 2020-05-28 09:40:49 +00:00
whitequark
5b62dbb0af
Merge pull request #2084 from rswarbrick/c_str 
Use c_str(), not str() for IdString/std::string == and != operators
 2020-05-28 09:40:35 +00:00
Alberto Gonzalez
5896ffd56f
printattrs: Simplify get_indent_str(). 
Co-Authored-By: Xiretza <xiretza@xiretza.xyz>
 2020-05-28 05:34:28 +00:00
Alberto Gonzalez
f671c99cb8
printattrs: Refactor indentation string building for clarity. 
Co-Authored-By: whitequark <whitequark@whitequark.org>
 2020-05-27 23:15:07 +00:00
Alberto Gonzalez
6228b10c9f
printattrs: Add test. 2020-05-27 08:00:00 +00:00
Alberto Gonzalez
e50e4ee285
printattrs: Use flags to pretty-print the RTLIL::Const appropriately. 
Co-Authored-By: whitequark <whitequark@whitequark.org>
 2020-05-27 08:00:00 +00:00
Alberto Gonzalez
b8365547e9
misc: Add printattrs command. 2020-05-27 08:00:00 +00:00
whitequark
b651352193
Merge pull request #2090 from whitequark/cxxrtl-fixes 
Minor fixes for CXXRTL
 2020-05-26 22:18:14 +00:00
whitequark
0bf6b164be cxxrtl: make logging a little bit nicer. 2020-05-26 21:37:32 +00:00
whitequark
e9c07e2bda cxxrtl: add missing parts of commit 281c9685. 2020-05-26 21:34:20 +00:00
Rupert Swarbrick
6aa0f72ae9 Silence spurious warning in Verilog lexer when compiling with GCC 
The chosen value shouldn't have any effect. I considered something
clearly wrong like -1, but there's no checking inside the generated
lexer, and I suspect this will cause even weirder bugs if triggered
than just setting it to INITIAL.
 2020-05-26 17:54:57 +01:00
Rupert Swarbrick
7ff306ccdb Minor optimisation in Module::wire() and Module::cell() 
The existing code does a search to figure out whether id is in the
dict (with the call to count()), and then looks it up again to get the
result (with the call to at()). This version calls find() instead,
avoiding the double lookup.

Code size increases slightly (6kb). I think this is because the
contents of find() are getting inlined, and then inlined into lots of
the callsites for cell() and wire().

Looking at the compiled code before this patch, you just get
a (non-inlined) call to count() followed by a call to at(). After the
patch, the contents of find() have been inlined (so you see do_hash,
then do_lookup). The result for each function is about 30 bytes / 40%
bigger, which presumably also enlarges call-sites that inline it.
 2020-05-26 16:07:36 +01:00
Rupert Swarbrick
17b5f23f20 Use default copy constructor for RTLIL::SigBit 
There was a handwritten copy constructor, which I'm not sure was
actually legal C++ (it unconditionally read from the 'data' member of
a union, which wouldn't have been written if wire was true). It was
also a bit less efficient than the constructor you get from the
compiler by default (which is allowed to just copy the memory).

This gives a marginal (~0.25%) decrease in code size when compiled
with GCC 9.3.
 2020-05-26 13:18:01 +01:00