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Author SHA1 Message Date
Paul Annesley
3efc14f5ad dfflegalize: remove redundant check for initialized dlatch 
This if condition is repeated verbatim, and I can't imagine a legitimate
way the inputs could change in between. I imagine it's a copy/paste
mistake.
 2021-10-17 22:10:37 +02:00
github-actions[bot]
0dd42d406d Bump version 2021-10-16 00:58:22 +00:00
Claire Xen
92ecfb2b36
Merge pull request #3044 from YosysHQ/micko/verific_bufif1 
Support PRIM_BUFIF1 primitive, fixes #2981
 2021-10-15 16:43:25 +02:00
Miodrag Milanovic
1aa6896966 Support PRIM_BUFIF1 primitive 2021-10-14 13:04:32 +02:00
github-actions[bot]
a0f5ba8501 Bump version 2021-10-12 00:57:44 +00:00
Claire Xen
2d3c79458d
Merge pull request #3039 from YosysHQ/claire/verific_aldff 
Add support for $aldff flip-flops to verific importer
 2021-10-11 10:01:56 +02:00
Claire Xenia Wolf
c8074769b0 Add Verific adffe/dffsre/aldffe FIXMEs 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-10-11 10:00:20 +02:00
Claire Xen
d5cc3a1c72
Merge pull request #3040 from YosysHQ/micko/split_module_ports 
Split module ports, 20 per line
 2021-10-11 09:56:05 +02:00
Claire Xen
c15b99c0de
Merge pull request #3041 from YosysHQ/mmicko/module_attr 
Import module attributes from Verific
 2021-10-11 09:54:28 +02:00
Miodrag Milanovic
93fbc9fba4 Import module attributes from Verific 2021-10-10 10:01:45 +02:00
Miodrag Milanovic
ff8e999a71 Split module ports, 20 per line 2021-10-09 13:40:55 +02:00
github-actions[bot]
d8f6d7b18d Bump version 2021-10-09 00:51:28 +00:00
Claire Xenia Wolf
34f1df8435 Fixes and add comments for open FIXME items 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-10-08 17:24:45 +02:00
Claire Xenia Wolf
1602a03864 Add support for $aldff flip-flops to verific importer 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-10-08 16:21:25 +02:00
Marcelina Kościelnicka
dc8da76282 Fix a regression from #3035. 2021-10-08 15:44:07 +02:00
github-actions[bot]
772b9a108a Bump version 2021-10-08 00:57:28 +00:00
Marcelina Kościelnicka
4e70c30775 FfData: some refactoring. 
- FfData now keeps track of the module and underlying cell, if any (so
  calling emit on FfData created from a cell will replace the existing cell)
- FfData implementation is split off to its own .cc file for faster
  compilation
- the "flip FF data sense by inserting inverters in front and after"
  functionality that zinit uses is moved onto FfData class and beefed up
  to have dffsr support, to support more use cases
 2021-10-07 04:24:06 +02:00
github-actions[bot]
356ec7bb39 Bump version 2021-10-05 00:53:24 +00:00
Miodrag Milanovic
abc5700628 verific set db_infer_set_reset_registers 2021-10-04 16:48:33 +02:00
github-actions[bot]
f3ef579ac4 Bump version 2021-10-03 00:58:23 +00:00
Marcelina Kościelnicka
e7d89e653c Hook up $aldff support in various passes. 2021-10-02 21:01:21 +02:00
Marcelina Kościelnicka
ba0723cad7 zinit: Refactor to use FfData. 2021-10-02 20:19:48 +02:00
Marcelina Kościelnicka
63b9df8693 kernel/ff: Refactor FfData to enable FFs with async load. 
- *_en is split into *_ce (clock enable) and *_aload (async load aka
  latch gate enable), so both can be present at once
- has_d is removed
- has_gclk is added (to have a clear marker for $ff)
- d_is_const and val_d leftovers are removed
- async2sync, clk2fflogic, opt_dff are updated to operate correctly on
  FFs with async load
 2021-10-02 20:19:48 +02:00
Marcelina Kościelnicka
ec2b5548fe Add $aldff and $aldffe: flip-flops with async load. 2021-10-02 18:12:52 +02:00
Zachary Snow
fbd70f28f0 Specify minimum bison version 3.0+ 
Yosys works with bison 3.0 (or newer), but not bison 2.7 (the previous
release). Ideally, we would require "3" rather than "3.0" to give a
better error message, but bison 2.3, which still ships with macOS, does
not support major-only version requirements. With this change, building
with an outdated bison yields: `frontends/rtlil/rtlil_parser.y:25.10-14:
require bison 3.0, but have 2.3`.
 2021-10-01 21:18:33 -06:00
Marcelina Kościelnicka
f9aad606ca simplemap: refactor to use FfData. 2021-10-02 03:24:57 +02:00
Miodrag Milanović
62739f7bf7
Merge pull request #3017 from YosysHQ/claire/short_rtlil_x_const 
Add optimization to rtlil back-end for all-x parameter values
 2021-09-28 18:03:14 +02:00
github-actions[bot]
7a7df9a3b4 Bump version 2021-09-28 00:53:49 +00:00
Miodrag Milanovic
070cad5f4b Prepare for next release cycle 2021-09-27 16:24:43 +02:00
Claire Xenia Wolf
89df26e4bc Add optimization to rtlil back-end for all-x parameter values 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-09-27 16:02:20 +02:00
github-actions[bot]
1cac671c70 Bump version 2021-09-25 00:51:53 +00:00
Claire Xen
0146d83ed8
Merge pull request #3014 from YosysHQ/claire/fix-vgtest 
Fix "make vgtest"
 2021-09-24 17:50:34 +02:00
Zachary Snow
9658d2e337 Fix TOK_ID memory leak in for_initialization 2021-09-23 13:33:55 -04:00
Claire Xenia Wolf
15fb0107dc Fix "make vgtest" so it runs to the end (but now it fails ;) 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-09-23 14:54:28 +02:00
github-actions[bot]
9432400ec8 Bump version 2021-09-22 00:54:54 +00:00
Zachary Snow
d6fe6d4fb6 sv: support wand and wor of data types 
This enables the usage of declarations of wand or wor with a base type
of logic, integer, or a typename. Note that declarations of nets with
2-state base types is still permitted, in violation of the spec.
 2021-09-21 14:52:28 -04:00
Zachary Snow
6b7267b849 verilog: fix multiple AST_PREFIX scope resolution issues 
- Root AST_PREFIX nodes are now subject to genblk expansion to allow
  them to refer to a locally-visible generate block
- Part selects on AST_PREFIX member leafs can now refer to generate
  block items (previously would not resolve and raise an error)
- Add source location information to AST_PREFIX nodes
 2021-09-21 12:10:59 -04:00
github-actions[bot]
3931b3a03f Bump version 2021-09-19 00:52:56 +00:00
Miodrag Milanović
e6766b950c
Merge pull request #3010 from the6p4c/master 
Fix protobuf backend build dependencies - intermittent build issue due to missing rule
 2021-09-18 09:16:58 +02:00
the6p4c
c25122e339 Fix protobuf backend build dependencies 
backends/protobuf/protobuf.cc depends on the source and header files
generated by protoc, but this dependency wasn't explicitly declared. Add
a rule to the Makefile to fix intermittent build failures when the
protobuf header/source file isn't built before protobuf.cc.
 2021-09-17 13:36:39 +10:00
github-actions[bot]
c88eaea6e0 Bump version 2021-09-14 00:56:06 +00:00
Marcelina Kościelnicka
551ef85cd7 verilog: Squash flex-triggered warning. 2021-09-13 18:58:17 +02:00
Miodrag Milanović
1d52c07e9b
Updates for CHANGELOG (#2997) 
Added missing changes from git log and  group items
 2021-09-13 16:25:42 +02:00
github-actions[bot]
f44110c625 Bump version 2021-09-11 00:50:11 +00:00
Miodrag Milanović
396918cc30
Merge pull request #3001 from YosysHQ/claire/sigcheck 
Add additional check to SigSpec
 2021-09-10 17:32:04 +02:00
Claire Xenia Wolf
4708907be8 Add additional check to SigSpec 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-09-10 16:51:34 +02:00
Marcelina Kościelnicka
33749f1e3a yosys-smtbmc: Fix reused loop variable. 
Fixes #2999.
 2021-09-10 13:34:58 +02:00
github-actions[bot]
1d61a911b7 Bump version 2021-09-10 00:55:14 +00:00
Eddie Hung
96b6410dcb
abc9: make re-entrant (#2993) 
* Add testcase

* Cleanup some state at end of abc9

* Re-assign abc9_box_id from scratch

* Suppress delete unless prep_bypass did something
 2021-09-09 10:06:31 -07:00
Eddie Hung
65316ec926
abc9: holes module to instantiate cells with NEW_ID (#2992) 
* Add testcase

* holes module to instantiate cells with NEW_ID
 2021-09-09 10:06:20 -07:00