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Import module attributes from Verific
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@ -917,6 +917,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
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} else {
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log("Importing module %s.\n", RTLIL::id2cstr(module->name));
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}
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import_attributes(module->attributes, nl, nl);
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SetIter si;
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MapIter mi, mi2;
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