mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-26 18:45:34 +00:00
Code Activity

Import module attributes from Verific

Browse source
This commit is contained in:
Miodrag Milanovic 2021-10-10 10:01:45 +02:00
parent d8f6d7b18d
commit 93fbc9fba4
1 changed files with 1 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

1
frontends/verific/verific.cc
View file

@ -917,6 +917,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
} else {
log("Importing module %s.\n", RTLIL::id2cstr(module->name));
}
import_attributes(module->attributes, nl, nl);
SetIter si;
MapIter mi, mi2;