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Code Activity
11619 commits 122 branches 59 tags 72 MiB
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430 commits

Author SHA1 Message Date
Jannis Harder
459941c8ff fmcombine: Add _gold/_gate suffix to memids 2022-06-03 21:52:28 +02:00
Mohamed A. Bamakhrama
1822be8792 Observe $TMPDIR variable when creating tmp files 
POSIX defines $TMPDIR as containing the pathname of the directory where
programs can create temporary files. On most systems, this variable points to
"/tmp". However, on some systems it can point to a different location.
Without respecting this variable, yosys fails to run on such systems.

Signed-off-by: Mohamed A. Bamakhrama <mohamed@alumni.tum.de>
 2022-05-27 15:06:53 +02:00
Miodrag Milanovic
8e02b3ca30 fix crash when no fst input 2022-05-04 11:21:39 +02:00
Miodrag Milanovic
ad48639cdd Start restoring memory state from VCD/FST 2022-05-04 10:41:04 +02:00
Miodrag Milanovic
3730db4b98 AIM file could have gaps in or between inputs and inits 2022-05-02 11:18:30 +02:00
Miodrag Milanovic
bbfdea2f8a Match $anyseq input if connected to public wire 2022-04-22 17:20:17 +02:00
Miodrag Milanovic
4d80bc24c7 Treat $anyseq as input from FST 2022-04-22 16:23:39 +02:00
Miodrag Milanovic
33f4009bb5 Last sample from input does not represent change 2022-04-22 13:46:11 +02:00
Miodrag Milanovic
83cad82b29 latches are always set to zero 2022-04-22 12:04:05 +02:00
Miodrag Milanovic
c989adcc2d If not multiclock, output only on clock edges 2022-04-22 12:03:39 +02:00
Miodrag Milanovic
75032a565d Set init state for all wires from FST and set past 2022-04-22 11:57:39 +02:00
Miodrag Milanovic
8fa2f3b260 Fix multiclock for btor2 witness 2022-04-22 11:53:41 +02:00
Miodrag Milanovic
9508bb2330 Fix reading aiw from other solvers 2022-04-15 11:45:16 +02:00
Miodrag Milanovic
868409361c Use wrap_async_control_gate if ff is fine 2022-04-08 16:30:29 +02:00
Iris Johnson
ccc6060f52 Makefile: properly conditionalize features requiring compression. 2022-04-07 20:07:44 -05:00
Miodrag Milanovic
6020ba67ac past_ad initial value setting 2022-04-02 19:13:15 +02:00
Miodrag Milanovic
2c96ecc5f7 setInitState can be only one altering values 2022-04-02 19:13:15 +02:00
Miodrag Milanovic
b54aecd80a Set past_d value for init state 2022-04-02 19:13:15 +02:00
Miodrag Milanovic
86ce441af6 Set init values for wrapped async control signals 2022-04-01 17:44:00 +02:00
Miodrag Milanovic
c95b9b4ba5 Support memories in aiw and multiclock 2022-03-31 13:10:13 +02:00
Miodrag Milanovic
322ab1cd54 Proper SigBit forming in sim 2022-03-22 14:43:18 +01:00
Miodrag Milanovic
ff3b0c2c46 Proper SigBit forming in sim 2022-03-22 14:22:32 +01:00
Miodrag Milanovic
55eed8df57 More verbose warnings 2022-03-18 14:47:35 +01:00
Miodrag Milanovic
1f3423cd7d Recognize registers and set initial state for them in tb 2022-03-16 14:35:39 +01:00
Miodrag Milanovic
e217e3017a Update sim help message. 2022-03-16 07:55:57 +01:00
Miodrag Milanovic
f5c20b8286 Added fst2tb pass for generating testbench 2022-03-14 19:06:29 +01:00
Miodrag Milanović
cbece4af0c
Merge pull request #3229 from YosysHQ/micko/sim_date 
Add date parameter to enable full date/time and version info
 2022-03-11 19:02:57 +01:00
Claire Xenia Wolf
e21badd4b3 Add "sim -q" option 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-03-11 16:26:11 +01:00
Miodrag Milanovic
37de369ba7 Add date parameter to enable full date/time and version info 2022-03-11 16:01:59 +01:00
Claire Xenia Wolf
be32de1caa Small fix in "sim" help message 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-03-11 15:36:23 +01:00
Miodrag Milanovic
5204694123 FstData already do conversion to VCD 2022-03-11 15:21:36 +01:00
Miodrag Milanovic
b72c779204 Support cell name in btor witness file 2022-03-11 15:11:14 +01:00
Miodrag Milanovic
357336339a Proper write of memory data 2022-03-11 11:19:53 +01:00
Miodrag Milanovic
295b0d1899 Start work on memory init 2022-03-09 18:34:02 +01:00
Miodrag Milanovic
f37ac5d934 Fixes and error check 2022-03-09 09:48:29 +01:00
Miodrag Milanovic
ede348cdc2 cleanup 2022-03-07 16:32:32 +01:00
Miodrag Milanovic
1b1ecd4ab0 Error checks for aiger witness 2022-03-07 15:00:14 +01:00
Miodrag Milanovic
b6aca1d743 btor2 witness co-simulation 2022-03-07 13:59:36 +01:00
Miodrag Milanović
9581b9adac
Merge pull request #3219 from YosysHQ/micko/quick_vcd 
VCD reader support by using external tool
 2022-03-04 10:42:14 +01:00
Miodrag Milanovic
59983eda17 Add option to ignore X only signals in output 2022-03-02 16:02:13 +01:00
Miodrag Milanovic
48b56a4f7f Write simulation files after simulation is performed 2022-03-02 15:23:07 +01:00
Miodrag Milanovic
28bc88a57e Cleanup 2022-03-02 09:39:22 +01:00
Miodrag Milanovic
94505395a9 Refactor sim output writers 2022-02-28 18:22:39 +01:00
Miodrag Milanovic
dfd4c81eac Quick fix 2022-02-28 11:40:06 +01:00
Claire Xenia Wolf
56b968f61c Add writing of aiw files to "sim" command 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-02-28 10:50:08 +01:00
Claire Xenia Wolf
1fd3a642c9 Hotfix in AIGER witness reader state machine 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-02-28 10:41:44 +01:00
Miodrag Milanovic
8be09b5b24 VCD reader support by using external tool 2022-02-28 09:09:07 +01:00
Miodrag Milanovic
9571acc0bf Support extended aiw format 2022-02-27 16:37:40 +01:00
Miodrag Milanovic
fca168797e Fix for last clock edge data 2022-02-25 16:15:32 +01:00
Claire Xenia Wolf
ca261d3c28 Experimental sim changes 2022-02-25 16:02:06 +01:00