8045 commits

This branch

This branch

All branches

Author	SHA1	Message	Date
Eddie Hung	3d98a96273	ifdef __ICARUS__ -> ifndef YOSYS	2020-01-01 17:33:10 -08:00
Eddie Hung	9e5ff30d05	Merge pull request #1606 from YosysHQ/eddie/improve_tests ... Fix a few issues in tests/arch/*	2020-01-01 13:31:46 -08:00
Eddie Hung	52fe1e0c44	Revert insertion of 'reg', leave note behind	2020-01-01 09:05:46 -08:00
Miodrag Milanović	6620b4e94e	Merge pull request #1605 from YosysHQ/iopad_fix ... iopad mapping should take care of existing io buffers	2020-01-01 17:46:45 +01:00
Eddie Hung	3deec51ddc	Fix anlogic async flop mapping	2020-01-01 08:43:16 -08:00
Miodrag Milanovic	a1344ec06e	Added a test case	2020-01-01 16:24:30 +01:00
Miodrag Milanovic	e0c879684f	take skip wire bits into account	2020-01-01 16:13:14 +01:00
Eddie Hung	713484fa66	Do not do call equiv_opt when no sim model exists	2019-12-31 18:40:30 -08:00
Eddie Hung	a59016b146	Fix warnings	2019-12-31 18:40:11 -08:00
Eddie Hung	c082329af3	Call equiv_opt with -multiclock and -assert	2019-12-31 18:39:32 -08:00
Eddie Hung	22fe931c86	Grammar	2019-12-30 15:07:15 -08:00
Eddie Hung	543bd2de6c	Update timings for Xilinx S7 cells	2019-12-30 14:36:07 -08:00
Miodrag Milanović	c0a17c2457	Merge pull request #1589 from YosysHQ/iopad_default ... Make iopad option default for all xilinx flows	2019-12-30 20:34:31 +01:00
Eddie Hung	c2c74f9bb0	Merge pull request #1599 from YosysHQ/eddie/retry_1588 ... Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once"	2019-12-30 10:01:02 -08:00
Eddie Hung	ce6e4f6341	Merge pull request #1600 from YosysHQ/eddie/cleanup_ecp5 ... Nitpick cleanup for ecp5	2019-12-30 10:00:47 -08:00
Miodrag Milanovic	f9749c202c	Fix new tests	2019-12-28 16:43:19 +01:00
Miodrag Milanovic	8c3de1d4bd	Merge remote-tracking branch 'origin/master' into iopad_default	2019-12-28 16:23:31 +01:00
Miodrag Milanovic	a82c701668	Make test without iopads	2019-12-28 16:22:24 +01:00
Miodrag Milanovic	509da7ed1a	Revert "Fix xilinx tests, when iopads are default" ... This reverts commit 477e43d921.	2019-12-28 16:12:45 +01:00
Eddie Hung	011f749ecf	Update resource count	2019-12-28 02:15:11 -08:00
Eddie Hung	71906fab51	Nitpick cleanup for ecp5	2019-12-27 16:57:08 -08:00
Eddie Hung	d45869855c	Add #1598 testcase	2019-12-27 16:44:57 -08:00
Eddie Hung	237415e78c	write_xaiger: inherit port ordering from original module	2019-12-27 16:44:18 -08:00
Eddie Hung	a56d6970f2	Revert "Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup" ... This reverts commit 92654f73ea, reversing changes made to 3e14ff1667.	2019-12-27 16:05:58 -08:00
Eddie Hung	9e6632c40a	Merge branch 'master' of github.com:YosysHQ/yosys	2019-12-27 15:37:26 -08:00
Eddie Hung	3d4644804e	write_xaiger: simplify c{i,o}_bits	2019-12-27 15:37:17 -08:00
David Shah	92654f73ea	Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup ... Revert "write_xaiger: only instantiate each whitebox cell type once"	2019-12-27 23:31:51 +00:00
David Shah	df31ade3b3	Revert "write_xaiger: only instantiate each whitebox cell type once"	2019-12-27 23:25:20 +00:00
Miodrag Milanovic	3e14ff1667	fixed invalid char	2019-12-25 20:38:48 +01:00
Marcin Kościelnicki	a24596def3	iopadmap: Emit tristate buffers with const OE for some edge cases.	2019-12-25 17:37:58 +01:00
Marcin Kościelnicki	13a3041030	Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen ... xilinx_dsp: Initial DSP48A/DSP48A1 support.	2019-12-25 16:18:44 +01:00
Marcin Kościelnicki	e226a8f7f1	Minor nit fixes	2019-12-25 15:39:40 +01:00
Eddie Hung	2e21aa59a2	Add DSP cascade tests	2019-12-23 14:58:06 -08:00
Eddie Hung	1d0ac659ad	Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too	2019-12-23 14:40:59 -08:00
Eddie Hung	75acaff6f5	Fix CEA/CEB check	2019-12-23 14:22:13 -08:00
Eddie Hung	edabe73377	Fix checking CE[AB] and for direct connections	2019-12-23 13:41:26 -08:00
Eddie Hung	71cac30309	Support unregistered cascades for A and B inputs	2019-12-23 12:38:18 -08:00
Eddie Hung	d00533eaa8	Add DSP48A* PCOUT -> PCIN cascade support	2019-12-23 11:42:46 -08:00
Marcin Kościelnicki	dadaf7ed78	xilinx: Test our DSP48A/DSP48A1 simulation models.	2019-12-23 20:36:43 +01:00
Marcin Kościelnicki	666c6128a9	xilinx_dsp: Initial DSP48A/DSP48A1 support.	2019-12-22 20:51:14 +01:00
Miodrag Milanovic	436fea9e69	Addressed review comments	2019-12-21 20:23:23 +01:00
Miodrag Milanovic	1937091f62	iopad no op for compatibility with old scripts	2019-12-21 13:21:45 +01:00
Miodrag Milanovic	477e43d921	Fix xilinx tests, when iopads are default	2019-12-21 13:18:44 +01:00
Miodrag Milanovic	2fcf683af4	Make iopad option default for all xilinx flows	2019-12-21 11:56:41 +01:00
Eddie Hung	aa1adb0f1e	Merge pull request #1588 from YosysHQ/eddie/xaiger_cleanup ... write_xaiger: only instantiate each whitebox cell type once	2019-12-20 14:56:08 -08:00
Eddie Hung	5986a4df40	Add abc9_arrival times for RAM{32,64}M	2019-12-20 14:06:59 -08:00
Eddie Hung	7928eb113c	Add RAM{32,64}M to abc9_map.v	2019-12-20 13:41:23 -08:00
Eddie Hung	ff2645ce0b	Put specify/endspecify inside ``	2019-12-20 13:38:32 -08:00
Eddie Hung	1482f32d53	Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lut ... Interpret "abc9 -lut" as lut string only if [0-9:]	2019-12-20 13:09:00 -08:00
Eddie Hung	a75e08c709	write_xaiger: only instantiate each whitebox cell type once	2019-12-20 13:07:24 -08:00