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	Merge pull request #1600 from YosysHQ/eddie/cleanup_ecp5
Nitpick cleanup for ecp5
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						ce6e4f6341
					
				
					 3 changed files with 6 additions and 14 deletions
				
			
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			@ -1,5 +1,6 @@
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// ---------------------------------------
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(* lib_whitebox *)
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module LUT4(input A, B, C, D, output Z);
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    parameter [15:0] INIT = 16'h0000;
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    wire [7:0] s3 = D ?     INIT[15:8] :     INIT[7:0];
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			@ -31,13 +32,8 @@ module CCU2C(
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	// First half
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	wire LUT4_0, LUT2_0;
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`ifdef _ABC
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	assign LUT4_0 = INIT0[{D0, C0, B0, A0}];
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	assign LUT2_0 = INIT0[{2'b00, B0, A0}];
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`else
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	LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
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	LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
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`endif
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	wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
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	assign S0 = LUT4_0 ^ gated_cin_0;
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			@ -46,13 +42,8 @@ module CCU2C(
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	// Second half
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	wire LUT4_1, LUT2_1;
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`ifdef _ABC
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	assign LUT4_1 = INIT1[{D1, C1, B1, A1}];
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	assign LUT2_1 = INIT1[{2'b00, B1, A1}];
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`else
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	LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
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	LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
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`endif
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	wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
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	assign S1 = LUT4_1 ^ gated_cin_1;
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			@ -209,6 +200,7 @@ endmodule
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// ---------------------------------------
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(* lib_whitebox *)
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module LUT2(input A, B, output Z);
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    parameter [3:0] INIT = 4'h0;
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    wire [1:0] s1 = B ?     INIT[ 3:2] :     INIT[1:0];
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			@ -230,7 +230,7 @@ struct SynthEcp5Pass : public ScriptPass
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	{
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		if (check_label("begin"))
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		{
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			run("read_verilog -D_ABC -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
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			run("read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
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			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
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		}
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			@ -39,8 +39,8 @@ proc
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux16 # Constrain all select calls below inside the top module
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select -assert-count 8 t:L6MUX21
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select -assert-count 26 t:LUT4
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select -assert-count 12 t:PFUMX
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select -assert-count 12 t:L6MUX21
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select -assert-count 34 t:LUT4
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select -assert-count 17 t:PFUMX
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select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
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